EP4384902A4 - Architecture de traitement parallèle faisant appel à des fichiers de registres distribués - Google Patents
Architecture de traitement parallèle faisant appel à des fichiers de registres distribuésInfo
- Publication number
- EP4384902A4 EP4384902A4 EP22856378.9A EP22856378A EP4384902A4 EP 4384902 A4 EP4384902 A4 EP 4384902A4 EP 22856378 A EP22856378 A EP 22856378A EP 4384902 A4 EP4384902 A4 EP 4384902A4
- Authority
- EP
- European Patent Office
- Prior art keywords
- parallel processing
- processing architecture
- registry files
- distributed registry
- distributed
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/76—Architectures of general purpose stored program computers
- G06F15/80—Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors
- G06F15/8007—Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors single instruction multiple data [SIMD] multiprocessors
- G06F15/8023—Two dimensional arrays, e.g. mesh, torus
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
- G06F3/0662—Virtualisation aspects
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F8/00—Arrangements for software engineering
- G06F8/40—Transformation of program code
- G06F8/41—Compilation
- G06F8/44—Encoding
- G06F8/441—Register allocation; Assignment of physical memory space to logical memory space
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F8/00—Arrangements for software engineering
- G06F8/40—Transformation of program code
- G06F8/41—Compilation
- G06F8/44—Encoding
- G06F8/447—Target code generation
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30098—Register arrangements
- G06F9/30101—Special purpose registers
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30098—Register arrangements
- G06F9/3012—Organisation of register space, e.g. banked or distributed register file
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
- G06F9/3838—Dependency mechanisms, e.g. register scoreboarding
- G06F9/384—Register renaming
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
- G06N20/00—Machine learning
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
- G06N3/00—Computing arrangements based on biological models
- G06N3/02—Neural networks
- G06N3/06—Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons
- G06N3/063—Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons using electronic means
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- Software Systems (AREA)
- General Physics & Mathematics (AREA)
- Computing Systems (AREA)
- Computer Hardware Design (AREA)
- Mathematical Physics (AREA)
- Biomedical Technology (AREA)
- Health & Medical Sciences (AREA)
- Artificial Intelligence (AREA)
- Life Sciences & Earth Sciences (AREA)
- Data Mining & Analysis (AREA)
- Evolutionary Computation (AREA)
- Biophysics (AREA)
- Molecular Biology (AREA)
- General Health & Medical Sciences (AREA)
- Computational Linguistics (AREA)
- Neurology (AREA)
- Computer Vision & Pattern Recognition (AREA)
- Medical Informatics (AREA)
- Human Computer Interaction (AREA)
- Advance Control (AREA)
- Devices For Executing Special Programs (AREA)
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US202163232230P | 2021-08-12 | 2021-08-12 | |
| PCT/US2022/033510 WO2023018477A1 (fr) | 2021-08-12 | 2022-06-15 | Architecture de traitement parallèle faisant appel à des fichiers de registres distribués |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| EP4384902A1 EP4384902A1 (fr) | 2024-06-19 |
| EP4384902A4 true EP4384902A4 (fr) | 2025-05-07 |
Family
ID=85200194
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| EP22856378.9A Withdrawn EP4384902A4 (fr) | 2021-08-12 | 2022-06-15 | Architecture de traitement parallèle faisant appel à des fichiers de registres distribués |
Country Status (3)
| Country | Link |
|---|---|
| EP (1) | EP4384902A4 (fr) |
| KR (1) | KR20240038109A (fr) |
| WO (1) | WO2023018477A1 (fr) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109325494B (zh) * | 2018-08-27 | 2021-09-17 | 腾讯科技(深圳)有限公司 | 图片处理方法、任务数据处理方法和装置 |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8949806B1 (en) * | 2007-02-07 | 2015-02-03 | Tilera Corporation | Compiling code for parallel processing architectures based on control flow |
Family Cites Families (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB201001621D0 (en) * | 2010-02-01 | 2010-03-17 | Univ Catholique Louvain | A tile-based processor architecture model for high efficiency embedded homogenous multicore platforms |
| KR102070199B1 (ko) * | 2012-05-11 | 2020-01-28 | 삼성전자주식회사 | 재구성가능 프로세서 및 재구성가능 프로세서의 코드 압축해제 방법 |
| US20150268963A1 (en) * | 2014-03-23 | 2015-09-24 | Technion Research & Development Foundation Ltd. | Execution of data-parallel programs on coarse-grained reconfigurable architecture hardware |
| US20160246602A1 (en) * | 2015-02-19 | 2016-08-25 | Arizona Board Of Regents On Behalf Of Arizona State University | Path selection based acceleration of conditionals in coarse grain reconfigurable arrays (cgras) |
| CN108364251B (zh) * | 2017-01-26 | 2021-06-25 | 超威半导体公司 | 具有通用寄存器资源管理的矢量处理器 |
-
2022
- 2022-06-15 WO PCT/US2022/033510 patent/WO2023018477A1/fr not_active Ceased
- 2022-06-15 EP EP22856378.9A patent/EP4384902A4/fr not_active Withdrawn
- 2022-06-15 KR KR1020247007624A patent/KR20240038109A/ko active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8949806B1 (en) * | 2007-02-07 | 2015-02-03 | Tilera Corporation | Compiling code for parallel processing architectures based on control flow |
Non-Patent Citations (3)
| Title |
|---|
| RYOO JIHYUN ET AL: "Leveraging parallelism in the presence of control flow on CGRAs", 2014 19TH ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE (ASP-DAC), IEEE, 20 January 2014 (2014-01-20), pages 285 - 291, XP032570086, DOI: 10.1109/ASPDAC.2014.6742904 * |
| See also references of WO2023018477A1 * |
| YUNG-CHIA LIN ET AL: "Effective Code Generation for Distributed and Ping-Pong Register Files: A Case Study on PAC VLIW DSP Cores", JOURNAL OF SIGNAL PROCESSING SYSTEMS ; FOR SIGNAL, IMAGE, AND VIDEO TECHNOLOGY (FORMERLY THE JOURNAL OF VLSI SIGNAL PROCESSING SYSTEMS FOR SIGNAL, IMAGE, AND VIDEO TECHNOLOGY), SPRINGER US, BOSTON, vol. 51, no. 3, 28 June 2007 (2007-06-28), pages 269 - 288, XP019616677, ISSN: 1939-8115 * |
Also Published As
| Publication number | Publication date |
|---|---|
| WO2023018477A1 (fr) | 2023-02-16 |
| KR20240038109A (ko) | 2024-03-22 |
| EP4384902A1 (fr) | 2024-06-19 |
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| RIC1 | Information provided on ipc code assigned before grant |
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| 18D | Application deemed to be withdrawn |
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