EP4384902A4 - Architecture de traitement parallèle faisant appel à des fichiers de registres distribués - Google Patents

Architecture de traitement parallèle faisant appel à des fichiers de registres distribués

Info

Publication number
EP4384902A4
EP4384902A4 EP22856378.9A EP22856378A EP4384902A4 EP 4384902 A4 EP4384902 A4 EP 4384902A4 EP 22856378 A EP22856378 A EP 22856378A EP 4384902 A4 EP4384902 A4 EP 4384902A4
Authority
EP
European Patent Office
Prior art keywords
parallel processing
processing architecture
registry files
distributed registry
distributed
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP22856378.9A
Other languages
German (de)
English (en)
Other versions
EP4384902A1 (fr
Inventor
Peter Foley
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Ascenium Inc
Original Assignee
Ascenium Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ascenium Inc filed Critical Ascenium Inc
Publication of EP4384902A1 publication Critical patent/EP4384902A1/fr
Publication of EP4384902A4 publication Critical patent/EP4384902A4/fr
Withdrawn legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00Digital computers in general; Data processing equipment in general
    • G06F15/76Architectures of general purpose stored program computers
    • G06F15/80Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors
    • G06F15/8007Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors single instruction multiple data [SIMD] multiprocessors
    • G06F15/8023Two dimensional arrays, e.g. mesh, torus
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601Interfaces specially adapted for storage systems
    • G06F3/0628Interfaces specially adapted for storage systems making use of a particular technique
    • G06F3/0662Virtualisation aspects
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F8/00Arrangements for software engineering
    • G06F8/40Transformation of program code
    • G06F8/41Compilation
    • G06F8/44Encoding
    • G06F8/441Register allocation; Assignment of physical memory space to logical memory space
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F8/00Arrangements for software engineering
    • G06F8/40Transformation of program code
    • G06F8/41Compilation
    • G06F8/44Encoding
    • G06F8/447Target code generation
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30098Register arrangements
    • G06F9/30101Special purpose registers
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30098Register arrangements
    • G06F9/3012Organisation of register space, e.g. banked or distributed register file
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3838Dependency mechanisms, e.g. register scoreboarding
    • G06F9/384Register renaming
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06NCOMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N20/00Machine learning
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06NCOMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N3/00Computing arrangements based on biological models
    • G06N3/02Neural networks
    • G06N3/06Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons
    • G06N3/063Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons using electronic means

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • General Physics & Mathematics (AREA)
  • Computing Systems (AREA)
  • Computer Hardware Design (AREA)
  • Mathematical Physics (AREA)
  • Biomedical Technology (AREA)
  • Health & Medical Sciences (AREA)
  • Artificial Intelligence (AREA)
  • Life Sciences & Earth Sciences (AREA)
  • Data Mining & Analysis (AREA)
  • Evolutionary Computation (AREA)
  • Biophysics (AREA)
  • Molecular Biology (AREA)
  • General Health & Medical Sciences (AREA)
  • Computational Linguistics (AREA)
  • Neurology (AREA)
  • Computer Vision & Pattern Recognition (AREA)
  • Medical Informatics (AREA)
  • Human Computer Interaction (AREA)
  • Advance Control (AREA)
  • Devices For Executing Special Programs (AREA)
EP22856378.9A 2021-08-12 2022-06-15 Architecture de traitement parallèle faisant appel à des fichiers de registres distribués Withdrawn EP4384902A4 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US202163232230P 2021-08-12 2021-08-12
PCT/US2022/033510 WO2023018477A1 (fr) 2021-08-12 2022-06-15 Architecture de traitement parallèle faisant appel à des fichiers de registres distribués

Publications (2)

Publication Number Publication Date
EP4384902A1 EP4384902A1 (fr) 2024-06-19
EP4384902A4 true EP4384902A4 (fr) 2025-05-07

Family

ID=85200194

Family Applications (1)

Application Number Title Priority Date Filing Date
EP22856378.9A Withdrawn EP4384902A4 (fr) 2021-08-12 2022-06-15 Architecture de traitement parallèle faisant appel à des fichiers de registres distribués

Country Status (3)

Country Link
EP (1) EP4384902A4 (fr)
KR (1) KR20240038109A (fr)
WO (1) WO2023018477A1 (fr)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109325494B (zh) * 2018-08-27 2021-09-17 腾讯科技(深圳)有限公司 图片处理方法、任务数据处理方法和装置

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8949806B1 (en) * 2007-02-07 2015-02-03 Tilera Corporation Compiling code for parallel processing architectures based on control flow

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB201001621D0 (en) * 2010-02-01 2010-03-17 Univ Catholique Louvain A tile-based processor architecture model for high efficiency embedded homogenous multicore platforms
KR102070199B1 (ko) * 2012-05-11 2020-01-28 삼성전자주식회사 재구성가능 프로세서 및 재구성가능 프로세서의 코드 압축해제 방법
US20150268963A1 (en) * 2014-03-23 2015-09-24 Technion Research & Development Foundation Ltd. Execution of data-parallel programs on coarse-grained reconfigurable architecture hardware
US20160246602A1 (en) * 2015-02-19 2016-08-25 Arizona Board Of Regents On Behalf Of Arizona State University Path selection based acceleration of conditionals in coarse grain reconfigurable arrays (cgras)
CN108364251B (zh) * 2017-01-26 2021-06-25 超威半导体公司 具有通用寄存器资源管理的矢量处理器

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8949806B1 (en) * 2007-02-07 2015-02-03 Tilera Corporation Compiling code for parallel processing architectures based on control flow

Non-Patent Citations (3)

* Cited by examiner, † Cited by third party
Title
RYOO JIHYUN ET AL: "Leveraging parallelism in the presence of control flow on CGRAs", 2014 19TH ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE (ASP-DAC), IEEE, 20 January 2014 (2014-01-20), pages 285 - 291, XP032570086, DOI: 10.1109/ASPDAC.2014.6742904 *
See also references of WO2023018477A1 *
YUNG-CHIA LIN ET AL: "Effective Code Generation for Distributed and Ping-Pong Register Files: A Case Study on PAC VLIW DSP Cores", JOURNAL OF SIGNAL PROCESSING SYSTEMS ; FOR SIGNAL, IMAGE, AND VIDEO TECHNOLOGY (FORMERLY THE JOURNAL OF VLSI SIGNAL PROCESSING SYSTEMS FOR SIGNAL, IMAGE, AND VIDEO TECHNOLOGY), SPRINGER US, BOSTON, vol. 51, no. 3, 28 June 2007 (2007-06-28), pages 269 - 288, XP019616677, ISSN: 1939-8115 *

Also Published As

Publication number Publication date
WO2023018477A1 (fr) 2023-02-16
KR20240038109A (ko) 2024-03-22
EP4384902A1 (fr) 2024-06-19

Similar Documents

Publication Publication Date Title
EP3953379A4 (fr) Compositions et méthodes de traitement du cancer faisant appel à une thérapie cellulaire par lymphocytes t à tet2 modifié
DK4204421T3 (da) Forbindelser og fremgangsmåder til behandling af virale infektioner
EP4004673A4 (fr) Systèmes et procédés de calcul analogique faisant appel à un processeur photonique linéaire
EP3732301A4 (fr) Méthodes de traitement du cancer faisant appel à un inhibiteur d'atr
EP3997594A4 (fr) Techniques de réutilisation de données matricielles dans des systèmes de traitement
EP4384902A4 (fr) Architecture de traitement parallèle faisant appel à des fichiers de registres distribués
MA46793A (fr) Polythérapies faisant appel à un inhibiteur d'arginase
EP3387128A4 (fr) Multiplexage en partitions faisant appel à des microparticules
EP4186616A4 (fr) Système de traitement
EP3463373A4 (fr) Polythérapies faisant appel à des modulateurs du récepteur de farnésoïde x (fxr)
EP3807033A4 (fr) Procédés de brasage destinés à assembler des céramiques et des métaux, et traitement de semi-conducteurs et équipement industriel mettant en oeuvre ces derniers
EP4297870A4 (fr) Compositions de neurotoxine à utiliser dans le traitement de la céphalée
EP4108802A4 (fr) Composant de traitement de chambre de réaction de pulvérisation et chambre de réaction de pulvérisation
EP3833310A4 (fr) Systèmes de traitement par forceps
EP4042721A4 (fr) Traitement de composantes audio spectralement orthogonales
EP3899768A4 (fr) Traitement sécurisé de vision par ordinateur
DK3989061T3 (da) Bit-pakket array-behandling ved anvendelse af simd
EP4425839A4 (fr) Traitement de paquets
EP4094126A4 (fr) Système, application logicielle et procédé d'assemblage lithographique
EP3575029A4 (fr) Tête de traitement laser et procédé de traitement laser faisant appel à ladite tête de traitement laser
EP3993729A4 (fr) Systèmes et procédés de guidage de traitement dentaire faisant appel à la réalité mixte
MA54088A (fr) Procédés de traitement faisant appel à des immunoconjugués anti-cd123
EP3463347A4 (fr) Dérivés de triazole benzamide et compositions et procédés de traitement associés
EP4314093A4 (fr) Composition adhésive (méth)acrylique durcissable par rayonnement
EP4264418A4 (fr) Architecture de traitement hautement parallèle utilisant une exécution à double ramification

Legal Events

Date Code Title Description
STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: THE INTERNATIONAL PUBLICATION HAS BEEN MADE

PUAI Public reference made under article 153(3) epc to a published international application that has entered the european phase

Free format text: ORIGINAL CODE: 0009012

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: REQUEST FOR EXAMINATION WAS MADE

17P Request for examination filed

Effective date: 20240306

AK Designated contracting states

Kind code of ref document: A1

Designated state(s): AL AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HR HU IE IS IT LI LT LU LV MC MK MT NL NO PL PT RO RS SE SI SK SM TR

DAV Request for validation of the european patent (deleted)
DAX Request for extension of the european patent (deleted)
REG Reference to a national code

Ref country code: DE

Ref legal event code: R079

Free format text: PREVIOUS MAIN CLASS: G06F0009380000

Ipc: G06F0015800000

A4 Supplementary search report drawn up and despatched

Effective date: 20250404

RIC1 Information provided on ipc code assigned before grant

Ipc: G06F 8/41 20180101ALI20250401BHEP

Ipc: G06F 15/80 20060101AFI20250401BHEP

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: THE APPLICATION IS DEEMED TO BE WITHDRAWN

18D Application deemed to be withdrawn

Effective date: 20251025