EP4399655A2 - Unités de traitement quantique modulaire à qubits logiques - Google Patents

Unités de traitement quantique modulaire à qubits logiques

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Publication number
EP4399655A2
EP4399655A2 EP22932460.3A EP22932460A EP4399655A2 EP 4399655 A2 EP4399655 A2 EP 4399655A2 EP 22932460 A EP22932460 A EP 22932460A EP 4399655 A2 EP4399655 A2 EP 4399655A2
Authority
EP
European Patent Office
Prior art keywords
quantum
quantum processor
chip
processor chips
qubit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
EP22932460.3A
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German (de)
English (en)
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EP4399655A4 (fr
Inventor
Matthew J. REAGOR
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Rigetti and Co LLC
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Rigetti and Co LLC
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Filing date
Publication date
Application filed by Rigetti and Co LLC filed Critical Rigetti and Co LLC
Publication of EP4399655A2 publication Critical patent/EP4399655A2/fr
Publication of EP4399655A4 publication Critical patent/EP4399655A4/fr
Pending legal-status Critical Current

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Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N10/00—Quantum computing, i.e. information processing based on quantum-mechanical phenomena
    • G06N10/40—Physical realisations or architectures of quantum processors or components for manipulating qubits, e.g. qubit coupling or qubit control
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N10/00—Quantum computing, i.e. information processing based on quantum-mechanical phenomena
    • G06N10/70—Quantum error correction, detection or prevention, e.g. surface codes or magic state distillation
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
    • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y10/00—Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N10/00—Quantum computing, i.e. information processing based on quantum-mechanical phenomena
    • G06N10/20—Models of quantum computing, e.g. quantum circuits or universal quantum computers
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N10/00—Quantum computing, i.e. information processing based on quantum-mechanical phenomena
    • G06N10/60—Quantum algorithms, e.g. based on quantum optimisation, quantum Fourier or Hadamard transforms

Definitions

  • FIG. 1 is a block diagram of an example computing environment.
  • FIG. 3 is a block diagram showing aspects of an example modular quantum processing unit.
  • a modular quantum processing unit includes multiple distinct quantum processor chips.
  • the quantum processor chips can be distinct hardware components that are coupled together, for example, across their boundaries.
  • the quantum processor chips may be designed, fabricated, tested, and selected individually, in batches, or otherwise.
  • each of the quantum processor chips may include distinct types of quantum circuit devices or functionalities.
  • quantum processor chips may be bonded (e.g., using bonding bumps, bonding pads, through-silicon signal vias, or a combination thereof) to a substrate (e.g., silicon, sapphire, etc.) in a modular quantum processing unit.
  • the substrate may include signal lines as well as coupler structures (e.g., superconducting traces or transmission lines) in or on the substrate that allow the quantum processor chips to communicate with each other and communicate with a control system.
  • FIG. 1 is a block diagram of an example computing environment 100.
  • the example computing environment 100 shown in FIG. 1 includes a computing system 101 and user devices 110A, HOB, HOC.
  • a computing environment may include additional or different features, and the components of a computing environment may operate as described with respect to FIG. 1 or in another manner.
  • the example computing system 101 can provide services to the user devices 110, for example, as a cloud-based or remote-accessed computer system, as a distributed computing resource, as a supercomputer or another type of high-performance computing resource, or in another manner.
  • the computing system 101 or the user devices 110 may also have access to one or more other quantum computing systems (e.g., quantum computing resources that are accessible through the wide area network 115, the local network 109, or otherwise].
  • the local network 109 may include one or more wired or wireless routers, wireless access points (WAPs), wireless mesh nodes, switches, high-speed cables, or a combination of these and other types of local network hardware elements.
  • the local network 109 includes a software-defined network that provides communication among virtual resources, for example, among an array of virtual machines operating on the server 108 and possibly elsewhere.
  • the remote user devices HOB, HOC operate remote from the servers 108 and other elements of the computing system 101.
  • the user devices 110B, HOC may be located at a remote distance (e.g., more than 1 km, 10 km, 100 km, 1,000 km, 10,000 km, or farther) from the servers 108 and possibly other elements of the computing system 101.
  • each of the user devices HOB, HOC communicates with the servers 108 through a remote data connection.
  • the remote data connection in FIG. 1 is provided by a wide area network 115, which may include, for example, the Internet or another type of wide area communication network.
  • remote user devices use another type of remote data connection (e.g., satellite-based connections, a cellular network, a virtual private network, etc.) to access the servers 108.
  • the wide area network 115 may include one or more internet servers, firewalls, service hubs, base stations, or a combination of these and other types of remote networking elements.
  • the computing environment 100 can be accessible to any number of remote user devices.
  • the example servers 108 shown in FIG. 1 can manage interaction with the user devices 110 and utilization of the quantum and classical computing resources in the computing system 101. For example, based on information from the user devices 110, the servers 108 may delegate computational tasks to the quantum computing systems 103A, 103B and the other resources 107; the servers 108 can then send information to the user devices 110 based on output data from the computational tasks performed by the quantum computing systems 103A, 103B, and the other resources 107.
  • the servers 108 are classical computing resources that include classical processors 111 and memory 112.
  • the servers 108 may also include one or more communication interfaces that allow the servers to communicate via the local network 109, the wide area network 115, and possibly other channels.
  • the servers 108 may include a host server, an application server, a virtual server, or a combination of these and other types of servers.
  • the servers 108 may include additional or different features, and may operate as described with respect to FIG. 1 or in another manner.
  • the classical processors 111 can include various kinds of apparatus, devices, and machines for processing data, including, by way of example, a microprocessor, a central processing unit (CPU), a graphics processing unit (GPU), an FPGA (field programmable gate array), an ASIC (application specific integrated circuit), or combinations of these.
  • the memory 112 can include, for example, a random-access memory (RAM), a storage device (e.g., a writable read-only memory (ROM) or others), a hard disk, or another type of storage medium.
  • the memory 112 can include various forms of volatile or non-volatile memory, media, and memory devices, etc.
  • Each of the example quantum computing systems 103A, 103B operates as a quantum computing resource in the computing system 101.
  • the other resources 107 may include additional quantum computing resources (e.g., quantum computing systems, quantum simulators, or both) as well as classical (non-quantum) computing resources such as, for example, digital microprocessors, specialized co-processor units (e.g., graphics processing units (GPUs), cryptographic co-processors, etc.), special purpose logic circuitry (e.g., field programmable gate arrays (FPGAs), application-specific integrated circuits (ASICs), etc.), systems-on-chips (SoCs), etc., or combinations of these and other types of computing modules.
  • quantum computing resources e.g., quantum computing systems, quantum simulators, or both
  • classical (non-quantum) computing resources such as, for example, digital microprocessors, specialized co-processor units (e.g., graphics processing units (GPUs), cryptographic co-processors, etc.), special
  • the servers 108 generate programs, identify appropriate computing resources (e.g., a QPU or QVM) in the computing system 101 to execute the programs, and send the programs to the identified resources for execution.
  • the servers 108 may send programs to the quantum computing system 103A, the quantum computing system 103B, or any of the other resources 107.
  • the programs may include classical programs, quantum programs, hybrid classical/quantum programs, and may include any type of function, code, data, instruction set, etc.
  • programs can be formatted as source code that can be rendered in human-readable form (e.g., as text) and can be compiled, for example, by a compiler running on the servers 108, on the quantum computing systems 103, or elsewhere.
  • programs can be formatted as compiled code, such as, for example, binary code (e.g., machine-level instructions) that can be executed directly by a computing resource.
  • Each program may include instructions corresponding to computational tasks that, when performed by an appropriate computing resource, generate output data based on input data.
  • a program can include instructions formatted for a quantum computer system, a simulator, a digital microprocessor, coprocessor or other classical data processing apparatus, or another type of computing resource.
  • quantum machine instructions maybe provided in a quantum instruction language such as Quil, described in the publication "A Practical Quantum Instruction Set Architecture,” arXiv:1608.03355v2, dated Feb. 17, 2017, or another quantum instruction language.
  • the quantum machine instructions may be written in a format that can be executed by a broad range of quantum processing units or simulators.
  • a program may be expressed in high-level terms of quantum logic gates or quantum algorithms, in lower-level terms of fundamental qubit rotations and controlled rotations, or in another form.
  • a program may be expressed in terms of control signals (e.g., pulse sequences, delays, etc.) and parameters for the control signals (e.g., frequencies, phases, durations, channels, etc.).
  • the servers 108 include one or more compilers that convert programs between formats.
  • the servers 108 may include a compiler that converts hardware-independent instructions to binary programs for execution by the quantum computing systems 103A, 103B.
  • a compiler can compile a program to a format that targets a specific quantum resource in the computer system 101.
  • a compiler may generate a different binary program (e.g., from the same source code) depending on whether the program is to be executed by the quantum computing system 103A or the quantum computing system 103B.
  • the cloud-based QC environment may be deployed in a "serverless" computing architecture.
  • the cloud-based QC environment may provide on-demand access to a shared pool of configurable computing resources (e.g., networks, servers, storage, applications, services, quantum computing resources, classical computing resources, etc.) that can be provisioned for requests from user devices 110.
  • the cloud-based computing systems 101 may include or utilize other types of computing resources, such as, for example, edge computing, fog computing, etc.
  • a logical qubit comprises a quantum register, for instance multiple physical qubits or qudits, and associated circuitry, that supports physical operations which can be used to detect or correct errors associated with logical states in a quantum algorithm.
  • Physical operations in a quantum logic circuit supported by the quantum register associated with a logical qubit may include single-qubit or multi-qubit quantum logic gates and readout operations. Error detection or correction mechanisms associated with a logical qubit may be based on quantum error correction schemes such as the surface code, color code, Bacon-Shor codes, low-density parity check codes (LDPC), some combination of these, or others.
  • a single quantum processor chip can be deployed as an individual hardware component, for example, a logical qubit die that can define one or more logical qubits.
  • logical qubits may actuate operations, such as those associated with lattice surgery, including MERGE or SPLIT operations, which temporarily delocalize logical qubits from specific physical qubit registers in order to perform multi-qubit operations, such as entangling quantum logic gates, between logical qubits, or to perform data movement operations of logical qubits. Nonetheless, quantum processor chips associated with individual tiles or patches of such schemes are recognizable as logical qubit dies if they may be initialized to support or operate individual logical qubits.
  • the quantum processing unit 102A may include, or may be deployed within, a controlled environment.
  • the controlled environment can be provided, for example, by shielding equipment, cryogenic equipment, and other types of environmental control systems.
  • the components in the quantum processing unit 102A operate in a cryogenic temperature regime and are subject to very low electromagnetic and thermal noise.
  • magnetic shielding can be used to shield the system components from stray magnetic fields
  • optical shielding can be used to shield the system components from optical noise
  • thermal shielding and cryogenic equipment can be used to maintain the system components at controlled temperature, etc.
  • the example quantum processing unit 102A can process quantum information by applying control signals to the qubits in the quantum processing unit 102A.
  • the control signals can be configured to encode information in the qubits, to process the information by performing quantum logic gates or other types of operations, or to extract information from the qubits.
  • the operations can be expressed as single-qubit quantum logic gates, two-qubit quantum logic gates, or other types of quantum logic gates that operate on one or more qubits.
  • a quantum logic circuit which includes a sequence of quantum logic operations, can be applied to the qubits to perform a quantum algorithm.
  • the quantum algorithm may correspond to a computational task, a hardware test, a quantum error correction procedure, a quantum state distillation procedure, or a combination of these and other types of operations.
  • the example control system 105A includes controllers 106A and signal hardware 104A.
  • control system 105B includes controllers 106B and signal hardware 104B. All or part of the control systems 105A, 105B can operate in a roomtemperature environment or another type of environment, which may be located near the respective quantum processing units 102A, 102B.
  • the control systems 105A, 105B include classical computers, signaling equipment (microwave, radio, optical, bias, etc.), electronic systems, vacuum control systems, refrigerant control systems, or other types of control systems that support operation of the quantum processing units 102A, 102B.
  • the control signals can be delivered to the quantum processing unit 102A during operation of the quantum computing system 103A.
  • the signal hardware 104A may generate signals to implement quantum logic operations, readout operations, or other types of operations.
  • the signal hardware 104A may include arbitrary waveform generators (AWGs) that generate electromagnetic waveforms [e.g., microwave or radio-frequency) or laser systems that generate optical waveforms.
  • AMGs arbitrary waveform generators
  • the waveforms or other types of signals generated by the signal hardware 104A can be delivered to devices in the quantum processing unit 102A to operate qubit devices, readout devices, bias devices, coupler devices, or other types of components in the quantum processing unit 102A.
  • the signal hardware 104A may include a digitizer that digitizes electromagnetic waveforms (e.g., microwave or radio-frequency) or optical signals, and a digitized waveform can be delivered to the controllers 106A or to other signal hardware components.
  • the controllers 106A process the information from the signal hardware 104Aand provide feedback to the signal hardware 104A; based on the feedback, the signal hardware 104A can in turn generate new control signals that are delivered to the quantum processing unit 102A.
  • the signal hardware 104A includes signal delivery hardware that interfaces with the quantum processing unit 102A.
  • the signal hardware 104A may include filters, attenuators, directional couplers, multiplexers, diplexers, bias components, signal channels, isolators, amplifiers, power dividers, and other types of components.
  • the signal delivery hardware performs preprocessing, signal conditioning, or other operations to the control signals to be delivered to the quantum processing unit 102A.
  • signal delivery hardware performs preprocessing, signal conditioning, or other operations on readout signals received from the quantum processing unit 102A.
  • the example controllers 106A communicate with the signal hardware 104Ato control operation of the quantum computing system 103A.
  • the controllers 106A may include classical computing hardware that directly interface with components of the signal hardware 104A.
  • the example controllers 106A may include classical processors, memory, clocks, digital circuitry, analog circuitry, and other types of systems or subsystems.
  • the classical processors may include one or more single- or multi-core microprocessors, digital electronic controllers, special purpose logic circuitry, e.g., an FPGA (field programmable gate array) or an ASIC (application specific integrated circuit), or other types of data processing apparatus.
  • the memory may include any type of volatile or non-volatile memory or another type of computer storage medium.
  • the controllers 106A may also include one or more communication interfaces that allow the controllers 106A to communicate via the local network 109 and possibly other channels.
  • the controllers 106A may include additional or different features and components.
  • the controllers 106A include memoiy or other components that store quantum state information, for example, based on qubit readout operations performed by the quantum computing system 103A.
  • quantum state information for example, based on qubit readout operations performed by the quantum computing system 103A.
  • the states of one or more qubits in the quantum processing unit 102A can be measured by qubit readout operations, and the measured state information can be stored in a cache or other type of memory system in one or more of the controllers 106A.
  • the measured state information is subsequently used in the execution of a quantum program, a quantum error correction procedure, a quantum processing unit (QPU) calibration or testing procedure, or another type of quantum process.
  • QPU quantum processing unit
  • the controllers 106A include memoiy or other components that store a quantum program containing quantum machine instructions for execution by the quantum computing system 103A. In some instances, the controllers 106A can interpret the quantum machine instructions and perform hardware-specific control operations according to the quantum machine instructions. For example, the controllers 106A may cause the signal hardware 104A to generate control signals that are delivered to the quantum processing unit 102A to execute the quantum machine instructions.
  • the controllers 106A extract qubit state information from qubit readout signals, for example, to identify the quantum states of qubits in the quantum processing unit 102A or for other purposes.
  • the controllers may receive the qubit readout signals (e.g., in the form of analog waveforms) from the signal hardware 104A, digitize the qubit readout signals, and extract qubit state information from the digitized signals.
  • the controllers 106A compute measurement statistics based on qubit state information from multiple shots of a quantum program. For example, each shot may produce a bitstring representing qubit state measurements for a single execution of the quantum program, and a collection of bitstrings from multiple shots may be analyzed to compute quantum state probabilities.
  • the controllers 106A include one or more clocks that control the timing of operations. For example, operations performed by the controllers 106A may be scheduled for execution over a series of clock cycles, and clock signals from one or more clocks can be used to control the relative timing of each operation or groups of operations. In some implementations, the controllers 106A may include classical computer resources that perform some or all of the operations of the servers 108 described above.
  • the controllers 106A may operate a compiler to generate binary programs (e.g., full or partial binary programs) from source code; the controllers 106A may include an optimizer that performs classical computational tasks of a hybrid classical/quantum program; the controllers 106A may update binary programs (e.g., at runtime) to include new parameters based on an output of the optimizer, etc.
  • binary programs e.g., full or partial binary programs
  • the controllers 106A may include an optimizer that performs classical computational tasks of a hybrid classical/quantum program
  • the controllers 106A may update binary programs (e.g., at runtime) to include new parameters based on an output of the optimizer, etc.
  • the other quantum computing system 103B and its components can be implemented as described above with respect to the quantum computing system 103A; in some cases, the quantum computing system 103B and its components maybe implemented or may operate in another manner.
  • the quantum computing systems 103A, 103B are disparate systems that provide distinct modalities of quantum computation.
  • the computer system 101 may include both an adiabatic quantum computing system and a gate-based quantum computer system.
  • the computer system 101 may include a superconducting circuit-based quantum computing system and an ion trap-based quantum computer system. In such cases, the computer system 101 may utilize each quantum computing system according to the type of quantum program that is being executed, according to availability or capacity, or based on other considerations.
  • FIG. 2 is a block diagram showing a perspective view of an example modular quantum processing unit 200.
  • the example modular quantum processing unit 200 includes one or more quantum processor modules 202.
  • the quantum processor modules 202 may be integrated on a common plate which includes inter-module coupler devices and other circuit element allowing the quantum processor modules to be communicab ly coupled to one another.
  • Each of the quantum processor modules 202 in the example modular quantum processing unit 200 includes an array of quantum processor chips 212.
  • neighboring pairs of quantum processor chips 202 are connected to each other through inter-chip circuit connections 206.
  • the inter-chip circuit connections 206 can include capacitive, inductive, or galvanic circuit connections, or combinations of these.
  • the inter-chip circuit connections 206 are provided by circuitry on the substrate 204, which is operably connected to ports, leads, bonds or other types of hardware interfaces on the respective quantum processor chips 212. Couplings provided by inter-chip circuit connections 206 can be used to apply multi-qubit quantum logic gates or other types of operations to qubits in distinct quantum processor chips.
  • the quantum logic gates mediated by inter-chip circuit connections 206 maybe used to provide entanglement between qubits in distinct quantum processor chips 212; in some cases, other schemes such as remote multi-qubit measurement can be used to entangle qubits in distinct quantum processor chips 212.
  • couplings provided by inter-chip circuit connections 206 can be used to apply quantum logic gates to logical qubits collectively defined by qubit devices on one or more respective quantum processor chips 212.
  • the quantum processor chips 212 of the quantum processor module 202 can be arranged on the substrate 204 as an array in a two-dimensional or three-dimensional lattice structure. Eleven of the quantum processor chips 212 in the quantum processor module 202 are shown in FIG. 2, but the quantum processor module 202 is scalable to include many more quantum processor chips (e.g., tens, hundreds, thousands, etc.). In some instances, a subset of the quantum processor chips may be supported on a common substrate 204.
  • a qubit device in the superconducting quantum circuit of a quantum processor chip 212 may be a fixed-frequency qubit device or a tunable-frequency qubit device.
  • the superconducting quantum circuit may also include coupler devices, readout resonator devices, or other types of quantum circuit devices.
  • each of the qubit devices in a quantum processor chip 212 can be encoded with a single bit of quantum information.
  • each of the qubit devices in a quantum processor chip 212 has two eigenstates that are used as computational basis states (e.g.,
  • the two lowest energy levels (e.g., the ground state and first excited state) of each qubit device are defined as a qubit and used as computational basis states for quantum computation.
  • higher energy levels e.g., a second excited state or a third excited state
  • Quantum states defined by respective qubit devices in a single quantum processor chip 212 can be manipulated by control signals, or read by readout signals, generated by a control system, e.g., the control system 504.
  • the qubit devices in a single quantum processor chip 212 can be controlled individually, for example, by delivering control signals from a control system to the respective qubit devices in the single quantum processor chip 212.
  • readout devices can detect the states of the qubit devices, for example, by interacting directly with the respective qubit devices.
  • each individual qubit device defines a single qubit
  • a lattice of qubit devices from the same quantum processor chip 212 or qubit devices from different quantum processor chips 212 when connected in an error check pattern, can operate collectively as a single logical qubit.
  • a stabilizer code or another type of quantum error correction scheme can be applied to the lattice of qubit devices, for example, by operation of a control system, according to the error check pattern.
  • one of the qubit devices operates as a data qubit device
  • other qubit devices in the lattice operate as ancilla (or parity-check qubit devices or stabilizer qubit devices, and a quantum error correction scheme is applied to the lattice of qubit devices.
  • all of the quantum processor chips 212 may include the same superconducting quantum circuit with the same circuit design and the same functionality.
  • two quantum processor chips 212 in the quantum processor module 202 may include identical circuit design, e.g., the same number of qubit devices, arrangements of signal lines, etc. In this case, two quantum processor chips 212 in the quantum processor module 202 may be fabricated through the same fabrication process.
  • the quantum processor chips 212 may include different superconducting quantum circuits with distinct circuit designs and distinct functionalities.
  • two quantum processor chips 212 in the quantum processor module 202 have different numbers of qubit devices, different connections (e.g., different intra-chip circuit connections) between qubit devices, different arrangements of signal lines, etc.
  • two quantum processor chips 212 in the quantum processor module 202 are fabricated using different fabrication processes.
  • multiple different fabrication processes are used to produce a batch of quantum processor chips 212.
  • design and fabrication processes of superconducting quantum circuits of different quantum processor chips 212 maybe separately optimized.
  • Example embodiments of the quantum processor chip data discussed above may include data indicative of these differences between the superconducting quantum circuits of the quantum processor chips.
  • the quantum processor chips 212 maybe evaluated, for example, using qubit frequency testing, optical micrograph analysis, gate performance testing, coherence time testing, and other types of testing.
  • the evaluations can be used to characterize the quantum processor chips according to their design specifications.
  • the quantum processor chips maybe categorized based on the evaluation results. For example, quantum processor chips may be sorted into multiple categories based on pre-determined criteria for each category. In some cases, the categories are indicative of a relative quality of a quantum processor chip. In some cases, the categories are indicative of a functionality of a quantum processor chip, the number of working qubit devices in a quantum processor chip 212, or a combination of these and other criteria. A subset of the quantum processor chips 212 may be selected from appropriate categories based on a specified performance level for the modular quantum processing unit 200.
  • the superconducting quantum circuit in a quantum processor chip 212 shown in FIG. 2 is fabricated on a substrate.
  • the substrate supporting the superconducting quantum circuit in a quantum processor chip 212 may be an elemental semiconductor, for example silicon germanium (Ge), selenium (Se), tellurium (Te), or another elemental semiconductor.
  • the substrate may also include a compound semiconductor such as aluminum oxide (sapphire), silicon carbide (SiC), gallium arsenic (GaAs), indium arsenide (InAs), indium phosphide (InP), silicon germanium (SiGe), silicon germanium carbide (SiGeC), gallium arsenic phosphide (GaAsP), gallium indium phosphide (GalnP), or another compound semiconductor.
  • the substrate may also include a superlattice with elemental or compound semiconductor layers.
  • the substrate includes an epitaxial layer.
  • the substrate may have an epitaxial layer overlying a bulk semiconductor or may include a semiconductor-on-insulator (SOI) structure.
  • SOI semiconductor-on-insulator
  • each of the superconductive layers may include a superconducting compound material, including superconducting metal nitrides and superconducting metal oxides, such as titanium-nitride (TiN), niobium-nitride (NbN), zirconium-nitride (ZrN), hafnium-nitride (HfN), vanadiumnitride (VN), tantalum-nitride (TaN), molybdenum-nitride (MoN), yttrium barium copper oxide (Y-Ba-Cu-O), or another superconducting compound material.
  • the superconducting quantum circuit in a quantum processor chip 212 may include multilayer superconductor-insulator heterostructures.
  • the superconducting quantum circuit in a quantum processor chip 212 is fabricated on the top surface of the substrate and patterned using a microfabrication process or in another manner.
  • quantum circuit devices in a superconducting quantum circuit of a quantum processor chip 212 may be formed by performing at least some of the following fabrication steps: using chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), spin-on coating, and/or other suitable techniques to deposit respective superconducting layers on the substrate; and performing one or more patterning processes (e.g., a lithography process, a dry /wet etching process, a soft/hard baking process, a cleaning process, etc.) to form openings in the respective superconducting layers.
  • CVD chemical vapor deposition
  • PVD physical vapor deposition
  • ALD atomic layer deposition
  • spin-on coating and/or other suitable techniques to deposit respective superconducting layers on the substrate
  • one or more patterning processes e.g.
  • a superconducting quantum circuit in each quantum processor chip 212 can operate as a logical qubit.
  • each quantum processor chip 212 operates a patch of surface code at distance 17.
  • the logical qubit is defined by the qubit devices in a single quantum processor chip 212 and includes approximately 577 qubits defined by the respective qubit devices of the single quantum processor chip 212.
  • the respective qubit devices in the quantum processor chip 212 are communicab ly coupled with an associated signal delivery system and local controllers (e.g., the signal delivery system 514 and the local controllers 516 shown in FIG. 5 or another control system) via respective control lines.
  • logic qubit errors at the boundary of quantum processor chips 212 can be decoded, incorporating specific properties of the inter-chip and intra-chip circuit connections.
  • a weighted graph decoder can assign higher weight values to connections corresponding to inter-chip error syndrome extraction which may have higher error rates due to more error prone inter-chip circuit connections. This may result in an overall higher effective physical error threshold, with the decoding task having the limiting case of decoding 2D syndrome graphs for perfect intra-chip error syndrome extraction.
  • decoding logical qubit errors allows for correlated error processes localized to one quantum processor chip 212.
  • the inter-chip circuit connections 206 on the substrate 204 are static low-dissipation connections.
  • an inter-chip circuit connection 206 may be a deterministic, low-loss wiring that can be configured to mediate coherent interactions between qubit devices from different quantum processor chips 212.
  • the deterministic, low-loss wiring may include, for example, superconducting transmission lines, phononic or photonic waveguides, through-silicon vias, amplifiers, nonreciprocal elements such as circulators or isolators, switches, or another type of structure.
  • the substrate 204 may further include a superconducting circuit that defines a switch network.
  • a switch network on the substrate 204 includes switch devices that determine a logical qubit connectivity graph, including relative orientation between quantum processor chips 212.
  • a quantum algorithm compilation includes configuring the switch network.
  • the modular quantum processing unit 200 includes multiple substrates 204, where each of the substrates 204 supports a subset of quantum processor chips 212 of the modular quantum processing unit 200. In this case, each of the substrates 204 includes a switch network that defines a portion of a logical qubit connectivity graph.
  • the substrate 204 may further include a plurality of qubit devices that can be communicably coupled to a subset of quantum processor chips 212 of the modular quantum processing unit 200.
  • the qubit devices on the substrate 204 may be used to facilitate stabilizer measurements between a subset of quantum processor chips 212, for instance by participating as ancilla qubit devices used to measure stabilizer information for data qubit devices spanning one or more quantum processor chips 212.
  • the substrate 204 may further include other circuit elements.
  • each quantum processor chip 212 is physically attached, bonded, or connected to the substrate 204. As shown in FIG. 2, the quantum processor chips 212 are bonded or attached to the substrate 204, for example, using bonding bumps.
  • each of the bonding bumps may include conductive or superconductive materials, such as copper or indium bumps.
  • the bonding bumps can provide electrical communication between the superconducting quantum circuits on the quantum processor chips 212 and the superconducting circuit on the substrate 204 (e.g., the inter-chip circuit connections 206.
  • quantum circuit devices in a superconducting quantum circuit of a quantum processor chip 212 may be communicably coupled, e.g., galvanically, capacitively, or inductively, to the circuitry on the substrate 204.
  • the substrate 204 can provide functional connections (e.g., the inter-chip circuit connections 206) between distinct quantum processor chips 212 in a quantum processor module 202 as well as connections between the quantum processor chips 212 and the external control system.
  • the superconducting circuit of the substrate 204 includes structures and circuit elements that provide control over the interactions between quantum circuit devices (e.g., qubit devices) in distinct quantum processor chips 212.
  • the superconducting circuit on the substrate 204 may include a variety of circuit elements to control or readout the qubit devices of the quantum processor chips 212 in the quantum processor module 202.
  • the superconducting circuit may include flux bias lines which can provide magnetic flux locally to tunable-frequency qubit devices to tune their frequencies.
  • the superconducting circuit may include tunable- frequency coupler devices, microwave feedlines, and resonator devices which are capacitively coupled to qubit devices to readout qubits.
  • the superconducting circuit on the substrate 204 may be formed in one or more electrically conductive layers.
  • each of the one or more electrically conductive layers may include a material that has normal conductance at the operating temperature of the example modular quantum processing unit 200.
  • the example modular quantum processing unit 200 can be operated at cryogenic temperatures (e.g., cooled using liquid helium) and each of the one or more electrically conductive layers (or at least a portion) can operate as a superconducting layer at that temperature.
  • quantum circuit devices in a quantum processor chip 212 may be coupled via alternative signal routing levels provided by the superconducting circuit on the substrate 204.
  • non-neighboring quantum circuit devices without qubit-to-qubit connections e.g., without direct intra-chip circuit connections on the quantum processor chip 212
  • the superconducting circuit on the substrate 204 may be coupled to the superconducting quantum circuit on a quantum processor chip 212 using capacitive, inductive, or galvanic circuit connections.
  • the superconducting circuit may include planar transmission lines, for example coplanar waveguides, substrate integrated waveguides, or another type of planar transmission line.
  • a subset of the one or more electrically conductive vias are electrically coupled with external signal lines, which are used to supply control signals to, or retrieve readout signals from, the quantum processor chips 212 of a quantum processor module 202.
  • the control signals can be provided to the quantum processor chips 212 from a signal delivery system (e.g., the signal delivery system 514 of the quantum computing system 500) or the readout signals can be retrieved from the quantum processor chips 212 to the signal delivery system, directly or through the substrate 204 of the quantum processor module 202.
  • the modular quantum processing unit 200 is an example of a multi-chip approach for superconducting qubit devices.
  • a full-stack system can be designed and operated to reflect the specific functionalities of the quantum processor chips 212 and substrates 204 as an additional efficiency.
  • End-user algorithms may be orchestrated on the modular quantum processing unit 200 via a control system (e.g., the global controller 508 in FIG. 5).
  • the control system may include a compiler providing compiled programs to the quantum processor chips.
  • FIG. 3 is a block diagram showing aspects of an example modular quantum processing unit 300.
  • the example modular quantum processing unit 300 includes multiple quantum processor chips on a substrate. As shown in FIG. 3, two of the multiple quantum processor chips are shown, e.g., a first quantum processor chip 302A and a second quantum processor chip 302B.
  • the first and second quantum processor chips 302A, 302B are two neighboring quantum processor chips on the substrate of the modular quantum processing unit 300. In some instances, the two quantum processor chips 302A, 302B may not be neighboring quantum processor chips.
  • the first and second quantum processor chips 302A, 302B are implemented as the quantum processor chip 212 in the example modular quantum processing unit 200 as shown in FIG. 2.
  • the example modular quantum processing unit 300 may include additional and different features or components, and components of the example modular superconducting quantum processing unit 300 may be implemented in another manner.
  • the parity-check qubit device 314A-1 of the first quantum processor chip 302A is communicably coupled to the boundary data qubit devices 312B-1 and 312B-2 on the second quantum processor chip 302B via respective inter-chip circuit connections 312;
  • the parity-check qubit device 314A-2 of the first quantum processor chip 302A is communicably coupled to the boundary data qubit devices 312B-3 and 312B-4 on the second quantum processor chip 302B via respective inter-chip circuit connections 312;
  • the parity-check qubit device 314B-1 of the second quantum processor chip 302B is communicably coupled to the boundary data qubit devices 312A-1 and 312A-2 on the first quantum processor chip 302A via respective inter-chip circuit connections 312;
  • the parity-check qubit device 314B-2 of the second quantum processor chip 302B is communicably coupled to the boundary data qubit devices 312A-3 and 312A-4 on the first quantum processor chip 302A via respective inter-chip circuit connections 312.
  • the intra-chip circuit connections 310A, 310B represent physical connections between qubit devices on the same quantum processor chip.
  • intra-chip circuit connections may include circuit elements such as static capacitive coupling elements or tunable-frequency coupler devices, that support two-qubit/qudit quantum logic gates.
  • the interchip circuit connections 312 (labeled in dashed lines) represent physical connections between qubit devices that reside on different quantum processor chips.
  • Square tiles in FIG. 3 represent different patterns of parity checks, for instance TLTL (tiles in dark gray) or XXXX (tiles in light gray) parity checks in the case of the standard surface code.
  • FIG. 4 is a schematic diagram of an example quantum error correction code (QECC) layout 400.
  • the example QECC layout 400 includes patches of quantum error correction codes defined on a 2D lattice of qubit devices of a quantum processor chip.
  • the example QECC layout 400 shown in FIG. 4 supports distance 5 surface code quantum error correction.
  • the distance is defined operationally as the number of physical errors that can accumulate before the logical state is corrupted beyond repair. Examples to define distance in surface code quantum error correction are described in the publication entitled “Surface codes: Towards practical large-scale quantum computation” by Fowler et al. (Phys. Rev. A 86, 032324, 2012), in the publication entitled “Low-distance Surface Codes under Realistic Quantum Noise” by Tomita et al. (arXiv: 1404.3747v3 [quant-ph], April 14, 2014), and in the publication entitled “Deep neural decoders for near term fault-tolerant experiments” by Chamberland et al.
  • the presence or absence of errors in the physical qubit devices can be detected as a change in the stabilizer measurement sequence, for instance observing (a -1) stabilizer outcome when (a +1) outcome is anticipated.
  • a decoding algorithm can be executed to determine what the most likely root-cause error is.
  • corrective action e.g., the application of quantum logic gates, or an update to the post-processing sequence, can be performed in response. Examples for performing quantum error correction are described in the publication entitled "Surface codes: Towards practical large-scale quantum computation” by Fowler et al. (Phys. Rev.
  • the quantum processor module 502 and all or part of the signal delivery systems 514, can be maintained in a controlled cryogenic environment.
  • the environment can be provided, for example, by shielding equipment, cryogenic equipment, and other types of environmental control systems.
  • the components in the quantum processor module 502 operate in a cryogenic temperature regime and are subject to very low electromagnetic and thermal noise.
  • magnetic shielding can be used to shield the system components from stray magnetic fields
  • optical shielding can be used to shield the system components from optical noise
  • thermal shielding and cryogenic equipment can be used to maintain the system components at controlled temperatures, etc.
  • information is encoded in the qubit devices in a quantum processor chip 512, and the information can be processed by operation of the qubit devices in the superconducting quantum circuit of the quantum processor chip 512.
  • input information can be encoded in the computational states or computational subspaces defined by some or all of the qubit devices in the quantum processor chip 512.
  • the input information can be processed, for example, by applying a quantum algorithm or other operations.
  • the local controller 516 sends control signals to the qubit devices in a quantum processor chip 512.
  • the control signals can be configured to manipulate the qubits defined by the qubit devices.
  • a control signal can be a direct current [DC] signal communicated from the local controller 516 to the individual qubit device.
  • a control signal can be an alternating current (AC) signal communicated from the local controller 516 to the individual qubit device.
  • the AC signal may be superposed with a direct current (DC) signal.
  • DC direct current
  • Other types of control signals may be used.
  • the local controller 516 identifies a quantum logic gate to be applied to qubit devices and possibly other quantum circuit devices in respective quantum processor chips 512.
  • the substrate 506 may include signal lines and circuit devices, which can be of the same type as the circuit devices on the quantum processor chips 512 (e.g., qubit devices, readout devices, etc.).
  • the substrate 506 may include bond pads which may be arranged such that each of the quantum processor chips 512 can be placed and bonded with good electrical contact and micron-scale alignment accuracy.
  • the quantum processor chip 512 may communicate with the circuit devices via the signal lines on the substrate 506.
  • the quantum processor chips 512 are also communicab ly coupled to one another via the signal lines or possibly the circuit devices on the substrate 506.
  • the signal lines 506 may be implemented as superconducting traces or other types of conductive structures. In some cases, the signal lines are routed three- dimensionally through the substrate 506 (e.g., through all or part of the thickness of the substrate 506), allowing for arbitrary connectivity architectures.
  • the substrate 506 may include a resonator bus which has many modes.
  • the resonator bus may allow for a higher bandwidth of coupling between the different quantum processor chips 512.
  • a bus of resonators may be used to couple qubit devices between different quantum processor chips 512 within a modular quantum processing unit 502.
  • the number of resonator modes in a resonator bus may determine the number of simultaneous two-qubit operations that are possible.
  • transmission lines can be routed in three dimensions within the substrate 506 allowing for a wider range of connectivity architectures, such that couplings can be generated between non-immediate-neighbor quantum processor chips, for example.
  • the substrate 506 may include ancilla qubit patches, each of which includes one or more ancilla qubit devices, associated control signal lines, and measurement circuitry.
  • an ancilla qubit patch can be initialized into the code, and used to fault-tolerantly extend or move quantum information across different quantum processor chips 512.
  • the substrate 506 may include deterministic, low-loss wiring to mediate coherent interactions between qubit devices from different quantum processor chips 512.
  • the deterministic, low-loss wiring may include, for example, superconducting transmission lines, phononic waveguides, or another type of structure.
  • the boundary qubit device may have higher connectivity than the intra-chip qubit devices (e.g., a total number of intra-chip circuit connections and inter-chip circuit connections of a boundary qubit device may be greater than four). This reduces the physical overhead and latency of operating the quantum processor module 502.
  • the substrate 506 may include multi-layer wiring, to facilitate signal routing and to achieve multiple module-to-module connections.
  • the substrate 506 includes a switch network that controls the inter-chip circuit connections among quantum processor chips 512.
  • the switch network may be a high-speed (e.g., nanoseconds) low-dissipation cryogenic switch network.
  • the switch network may include switches that are Josephson junction-based which includes SQUID loops.
  • switches of the switch network may be transistor-based, e.g., complementary metal-oxide-semiconductor (CMOS) devices or high-electron mobility transistor (HEMT) devices.
  • CMOS complementary metal-oxide-semiconductor
  • HEMT high-electron mobility transistor
  • the switch network can reduce the physical overhead of the quantum processor module 502 by improving on typical planar connectivity of qubit devices for superconducting processors.
  • connections provided by the switch network between quantum processor chips 512 can be configured by the global controller 508 and may be modified during operation of the modular quantum processing unit, for example when executing a quantum algorithm. Multiple relative orientations between quantum processor chips 512 may also be supported to reduce the need for rotating logical qubits.
  • a switch network toggles coupling between qubit devices on the boundaries of quantum processor chips 512, rather than all of possible combinations of qubit devices on the multi-chip processor.
  • This feature may be attractive for logical qubit algorithms spanning a plurality of quantum processor chips 512 because the boundary qubit devices are the ones that are deployed for logical qubit entanglement methods, such as lattice surgery, rather than all of the qubit devices in the quantum processor chips 512.
  • Separate quantum processor chips are an important enabler for switch-based technologies since these can generate nonequilibrium quasiparticles (e.g., SQUIDs) or are a different manufacturing process than what is typically used for superconducting qubit devices (e.g., HEMT).
  • switches in a switch network may enable multiple inter-chip circuit connections within a clock cycle of a quantum error correction scheme to facilitate high-weight parity check operations.
  • the switch network may not be supported by the substrate 506.
  • the switch network may be a part of the control system located at an elevated temperature.
  • the substrate 506 can interface with the switch network or communicate with the switch network in another manner.
  • the switch network may be implemented as the switch network 604 in FIG. 6 or in another manner.
  • the global controller 508 and the local controllers 516 are optimized for the modular quantum processing unit 502 by localizing computing/signal processing/ signal generation to reflect the configuration of individual quantum processor chip 512 (e.g., high-speed, low-latency distributed computations and communication between qubit devices on a respective quantum processor chip 512 and a respective local controller 516).
  • the switch network on the substrate 506 providing inter-chip circuit connections between quantum processor chips 502 includes cryogenic switches operating in a cryogenic environment.
  • the computing system 500 includes one or more decoders associated with the quantum processor chips 512 of the quantum processor module 502.
  • the one or more decoders are configured to process error syndromes when applying quantum error correction according to properties of inter-chip or intra-chip circuit connections. For example, if inter-chip circuit connections in a region of a quantum processor module 502 where multiple quantum processor chips 512 are connected have much higher error rates, decoders can emphasize this region. For example, a higher threshold value of the effective error can be assigned for these inter-chip circuit connections, since the ID boundary is a lower-dimensional problem.
  • a decoder allows for one quantum processor chip 512 to suffer an irrecoverable error.
  • FIG. 6 is a schematic diagram showing aspects of an example quantum processor module 600.
  • the example quantum processor module 600 includes multiple quantum processor chips 602 on a substrate 606. As shown in FIG. 6, two of the multiple quantum processor chips are shown, e.g., a first quantum processor chip 602A and a second quantum processor chip 602B.
  • the first and second quantum processor chip 602A, 602B are two neighboring quantum processor chips on the modular quantum processing unit 600. In some instances, the two quantum processor chips are not neighboring quantum processor chips.
  • the first and second quantum processor chips 602A, 602B are implemented as the quantum processor chip 212 in the example modular quantum processing unit 200 as shown in FIG. 2.
  • the substrate 606 may be implemented as the substrate 204, 506 in FIGS. 2, 5 or in another manner.
  • the example quantum processor module 600 may include additional and different features or components, and components of the example quantum processor module 600 may be implemented in another manner.
  • each of the first and second quantum processor chips 602A, 602 B includes a superconducting quantum circuit with multiple quantum circuit devices (e.g., qubit devices, coupler devices, readout devices, etc.) and connections.
  • each of the first and second quantum processor chips 602A, 602B includes data qubit devices (labeled as “unfilled” circles in FIG. 6), parity-check qubit device (labeled as "filled” circles in FIG. 6), and intra-chip circuit connections (solid lines between circles in FIG. 6). Couplings provided by intra-chip circuit connections 310A, 310B can be used to apply multi-qubit quantum logic gates or other types of operations to qubits defined by qubit devices within the same quantum processor chip.
  • Quantum logic gates mediated by intra- chip circuit connections can be used to create entanglement between qubits defined by qubit devices within the same quantum processor chip.
  • the quantum processor chips 602A, 602B can be implemented as the quantum processor chips 302A, 302B in FIG. 3 or in another manner.
  • the first and second quantum processor chips 602A, 602B are connected via a switch network 604 with multiple switches 612.
  • the switch network 604 is a cryogenic switch network, for example, supported on the substrate 606, which operates together with the quantum processor chips 602A, 602B at a cryogenic temperature.
  • the switch network 604 is a 1:2 switch matrix.
  • the parity-check qubit devices (filled circles) along one die boundary of the first quantum processor chip 602A are connected to the parity-check qubit devices along two neighboring die boundaries of the second quantum processor chip 602B through the switch network 604.
  • the switch network 604 enables inter-chip circuit connections between logical qubits collectively defined by respective qubit devices of the two quantum processor chips 602A, 602B, for instance through lattice surgery.
  • the switch network 604 defines the relative orientation between the logical qubits.
  • logical Z operators are defined along one axis (e.g., Y-axis) within each quantum processor chip and logical X operators are defined along an orthogonal axis (e.g., X-axis)
  • X-axis an orthogonal axis
  • Common techniques for achieving general two-qubit quantum logic gates between the logical qubits would require rotating the basis for one or more of these qubit devices, changing the assignment of logical operator to effective physical axis for one or more logical qubits, relative to a subset of other logical qubits.. This can be done over several effective clock cycles using initialization and measurement steps.
  • an effective rotation in zero clock cycles is achieved by operation of the switch network.
  • an effective rotation can be achieved by toggling between relative orientations, by operation of the switch devices 612 of the switch network 604.
  • the switches 612 are supported on the substrate 606, and their states (e.g., directionality) are determined and controlled by receiving control signals from the external control system.
  • the external control system may include a compiler.
  • the compiler is used to determine strategies and sequences of inter-chip circuit connections between the quantum processor chips 602A, 602B to optimize the execution of a quantum algorithm, e.g., by increasing parallelism.
  • the connections for example, defined by the switch devices 612 of the switch network 604 is controlled by operation of the control system according to the quantum algorithm for processing quantum information.
  • the connectivity of the quantum processor chips 602A, 602B, as well as connectivity to other quantum processor chips within the example quantum processor module 600 can be tracked and updated at a clock cycle time compatible with the speed of executing quantum logic gates on the quantum processor chips 602A, 602B of the quantum processor module 600.
  • Some of the subject matter and operations described in this specification can be implemented in digital electronic circuitry, or in computer software, firmware, or hardware, including the structures disclosed in this specification and their structural equivalents, or in combinations of one or more of them.
  • Some of the subject matter described in this specification can be implemented as one or more computer programs, i.e., one or more modules of computer program instructions, encoded on a computer storage medium for execution by, or to control the operation of, data-processing apparatus.
  • a computer storage medium can be, or can be included in, a computer-readable storage device, a computer-readable storage substrate, a random or serial access memory array or device, or a combination of one or more of them.
  • a computer storage medium is not a propagated signal
  • a computer storage medium can be a source or destination of computer program instructions encoded in an artificially generated propagated signal.
  • the computer storage medium can also be, or be included in, one or more separate physical components or media.
  • the term "data-processing apparatus” encompasses all kinds of apparatus, devices, and machines for processing data, including by way of example a programmable processor, a computer, a system on a chip, or multiple ones, or combinations, of the foregoing.
  • the apparatus can include special purpose logic circuitry, e.g., an FPGA (field programmable gate array] or an ASIC (application specific integrated circuit].
  • the apparatus can also include, in addition to hardware, code that creates an execution environment for the computer program in question, e.g., code that constitutes processor firmware, a protocol stack, a database management system, an operating system, a crossplatform runtime environment, a virtual machine, or a combination of one or more of them.
  • a computer program (also known as a program, software, software application, script, or code] can be written in any form of programming language, including compiled or interpreted languages, declarative or procedural languages, and it can be deployed in any form, including as a stand-alone program or as a module, component, subroutine, object, or other unit suitable for use in a computing environment.
  • a computer program may, but need not, correspond to a file in a file system.
  • a program can be stored in a portion of a file that holds other programs or data (e.g., one or more scripts stored in a markup language document], in a single file dedicated to the program, or in multiple coordinated files (e.g., files that store one or more modules, sub programs, or portions of code].
  • a computer program can be deployed to be executed on one computer or on multiple computers that are located at one site or distributed across multiple sites and interconnected by a communication network.
  • a computing system includes a modular quantum processing unit and a control system communicably coupled to the modular quantum processing unit.
  • the modular quantum processing unit includes a plurality of quantum processor chips, and a substrate that supports the plurality of quantum processor chips.
  • Each quantum processor chip includes a superconducting quantum circuit; and each superconducting quantum circuit includes quantum circuit devices and intra-chip circuit connections between respective pairs of the quantum circuit devices within the superconducting quantum circuit.
  • the quantum circuit devices include a plurality of qubit devices.
  • the substrate includes circuitry which includes inter-chip circuit connections between respective pairs of the quantum circuit devices across distinct superconducting quantum processor chips.
  • the control system is configured to process quantum information by operation of the modular quantum processing unit.
  • the control system is configured to process the quantum information by processing logical qubits, and operation of the modular quantum processing unit includes a definition of each of the logical qubits on a respective subset of the plurality of quantum processor chips; and an application of quantum error correction to the logical qubits defined by each respective subset of the plurality of quantum processor chips.
  • a definition of a logical qubit may refer to data or circuitry that maps or otherwise associates a logical qubit to the physical qubit devices that may reside on one or more quantum processor chips.
  • the definition may map a logical qubit to each of the physical qubits in a quantum processor chip.
  • the definition may map a logical qubit to a subset of physical qubits in a quantum processor chip.
  • the definition may map a logical qubit to physical qubits located in two or more quantum processor chips.
  • Implementations of the first example may include one or more of the following features.
  • the plurality of qubit devices in each superconducting quantum circuit is connected in an error check pattern.
  • the control system is configured to apply a quantum error correction scheme to each superconducting quantum circuit based on the error check pattern.
  • the quantum error correction scheme includes a surface code or a color code.
  • Implementations of the first example may include one or more of the following features.
  • the plurality of quantum processor chips is bonded to the substrate.
  • the interchip circuit connections include at least one of capacitive, inductive, or galvanic circuit connections.
  • the control system includes a global controller and a plurality of local controllers; and each of the quantum processor chips is associated with a respective one of the plurality of local controllers.
  • the control system includes a plurality of signal delivery systems; and each of the plurality of signal delivery systems delivers signals between a respective one of the quantum processor chips and its associated local controller.
  • Implementations of the first example may include one or more of the following features.
  • the control system is configured to modify the respective inter-chip circuit connections during operation of the modular quantum processing unit.
  • the substrate includes a switch network that controls the inter-chip circuit connections and defines a logical qubit connectivity graph.
  • the switch network includes a cryogenic switch network.
  • the switch network includes a plurality of switch devices configured to enable at least a subset of the inter-chip circuit connections within a clock cycle of a quantum error correction scheme.
  • the control system is configured to process the quantum information based on applying a quantum algorithm; and controlling the switch network according to the quantum algorithm.
  • Implementations of the first example may include one or more of the following features.
  • the inter-chip circuit connections mediate coherent interactions between qubit devices in distinct quantum processor chips.
  • the quantum processor chips reside in a cryogenic environment at a first temperature; and the control system includes a switch network residing in a distinct environment at a second temperature greater than the first temperature.
  • the control system is configured to process the quantum information based on applying a quantum logic circuit to the logical qubits; and the quantum logic circuit includes single-qubit quantum logic gates, multi-qubit quantum logic gates, and readout operations.
  • Implementations of the first example may include one or more of the following features.
  • Each of the quantum processor chips includes boundary qubit devices; and the boundary qubit devices of distinct quantum processor chips are connected to each other by the inter-chip circuit connections.
  • Each of the quantum processor chips includes paritycheck qubit devices; and application of the quantum error correction includes operation of the parity-check qubit devices to perform parity check operations.
  • the respective subset of the plurality of quantum processor chip is a quantum processor chip or multiple quantum processor chips.
  • a computing system includes a first subset of quantum processor chips, a second subset of quantum processor chips, and a substrate.
  • the first subset of quantum processor chips includes first superconducting quantum circuits.
  • Each of the first superconducting quantum circuits includes a first set of qubit devices.
  • the first superconducting quantum circuits are configured to support a first logical qubit operated according to a first quantum error correction scheme.
  • the second subset of quantum processor chips includes second superconducting quantum circuits.
  • Each of the second superconducting quantum circuits includes a second set of qubit devices.
  • the second superconducting quantum circuits are configured to supporta second logical qubit operated according to a second quantum error correction scheme.
  • the substrate is configured to support the firstand second subsets of quantum processor chips and includes inter-chip connections between the firstand second superconducting quantum circuits.
  • the computing system includes a control system communicably coupled to the first and second subsets of quantum processor chips.
  • the control system is configured to process quantum information based on operation of the firstand second subsets of quantum processor chips.
  • the control system is configured to process the quantum information based on processing the first and second logical qubits; and operating the firstand second subsets of quantum processor chips includes an application of the first and second quantum error correction schemes to the first and second logical qubits.
  • Each of the firstand second quantum error correction schemes includes a surface code or a color code.
  • the substrate includes a switch network that controls the inter-chip circuit connections and defines a logical qubit connectivity graph.
  • Each of the first and second subsets of quantum processor chips is a quantum processor chip or multiple quantum processor chips.
  • a computer-readable medium includes first quantum processor chip data and second quantum processor chip data.
  • the first quantum processor chip data characterizes a first subset of quantum processor chips; and the second quantum processor chip data characterizes a second subset of quantum processor chips.
  • the first quantum processor chips include first superconducting quantum circuits.
  • the first superconducting quantum circuits are configured to support a first logical qubit operated according to a first quantum error correction scheme.
  • the second quantum processor chips include second superconducting quantum circuits.
  • the second superconducting quantum circuits are configured to support a second logical qubit operated according to a second quantum error correction scheme.
  • the firstand the second subsets of quantum processor chips are supported on a substrate with inter-chip circuit connections between the first and the second superconducting quantum circuits.
  • Implementations of the third example may include one or more of the following features.
  • the first quantum processor chip includes first quantum circuit devices; and the second quantum processor chip includes second quantum circuit devices.
  • the first quantum processor chip includes first intra-chip circuit connections between respective pairs of the first quantum circuit devices; and the second quantum processor chip includes second intra-chip circuit connections between respective pairs of the second quantum circuit devices.
  • Each of the first and second quantum error correction schemes includes a surface code or a color code.
  • the substrate includes a switch network that controls the inter-chip circuit connections and defines a logical qubit connectivity graph.
  • Each of the first and second subsets of quantum processor chips is a quantum processor chip or multiple quantum processor chips.
  • a computing system includes a modular quantum processing unit including a plurality of quantum processor chips and means for operating the modular quantum processing unit based on logical qubits.
  • a modular quantum processing unit including a plurality of quantum processor chips and means for operating the modular quantum processing unit based on logical qubits.
  • Each of the logical qubits is supported by a respective subset of the plurality of quantum processor chips.
  • Implementations of the fourth example may include one or more of the following features.
  • Each quantum processor chip includes a superconducting quantum circuit, and each superconducting quantum circuit includes quantum circuit devices including a plurality of qubit devices, and intra-chip circuit connections between respective pairs of the quantum circuit devices within the superconducting quantum circuit.
  • the modular quantum processing unit includes a substrate that supports the plurality of respective quantum processor chips and includes circuitry.
  • the circuitry includes inter-chip circuit connections between respective pairs of the quantum circuit devices in distinct quantum processor chips.
  • the substrate includes a switch network that controls the inter-chip circuit connections and defines a logical qubit connectivity graph.
  • the means for operating modular quantum processing unit includes a control system communicably coupled to the modular quantum processing unit. The control system is configured to process quantum information based on operation of the modular quantum processing unit.
  • the control system is configured to process the quantum information based on processing logical qubits; and operating the modular quantum processing unit is based on a definition of the logical qubits on the respective quantum processor chips; and an application of quantum error correction to a logical qubit defined by each respective quantum processor chip.
  • the respective subset of the plurality of quantum processor chips is a quantum processor chip or multiple quantum processor chip.

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Abstract

Dans un aspect général, l'invention concerne une unité de traitement quantique modulaire comprenant des modules matériels de traitement quantique. Dans certains modes de réalisation, un système informatique comprend une unité de traitement quantique modulaire et un système de commande couplé en termes de communication à l'unité de traitement quantique modulaire. L'unité de traitement quantique modulaire comprend des puces processeurs quantiques, et un substrat qui supporte les puces processeurs quantiques. Chaque puce processeur quantique comprend un circuit quantique supraconducteur ; et chaque circuit quantique supraconducteur comprend des dispositifs de circuit quantique et des connexions de circuit intra-puce entre des paires respectives des dispositifs de circuit quantique à l'intérieur du circuit quantique supraconducteur. Les dispositifs de circuit quantique comprennent une pluralité de dispositifs à qubits. Le substrat comprend des circuits qui comprennent des connexions de circuit inter-puce entre des paires respectives des dispositifs de circuit quantique dans des puces processeurs quantiques supraconductrices distinctes. Le système de commande est conçu pour traiter des informations quantiques par le fonctionnement de l'unité de traitement quantique modulaire. Le système de commande est conçu pour traiter les informations quantiques par traitement de qubits logiques, et le fonctionnement de l'unité de traitement quantique modulaire comprend la définition de chacun des qubits logiques sur un sous-ensemble respectif des puces processeurs quantiques ; et l'application d'une correction d'erreur quantique aux qubits logiques définis par chaque sous-ensemble respectif des puces processeurs quantiques.
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