EP4702597A1 - Structure d'encapsulation de niveau de panneau à interconnexions entièrement parallèles - Google Patents

Structure d'encapsulation de niveau de panneau à interconnexions entièrement parallèles

Info

Publication number
EP4702597A1
EP4702597A1 EP23735996.3A EP23735996A EP4702597A1 EP 4702597 A1 EP4702597 A1 EP 4702597A1 EP 23735996 A EP23735996 A EP 23735996A EP 4702597 A1 EP4702597 A1 EP 4702597A1
Authority
EP
European Patent Office
Prior art keywords
package
bond
semiconductor die
contact
sheets
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
EP23735996.3A
Other languages
German (de)
English (en)
Inventor
Lasse Petteri PALM
Andreas Munding
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Huawei Digital Power Technologies Co Ltd
Original Assignee
Huawei Digital Power Technologies Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Huawei Digital Power Technologies Co Ltd filed Critical Huawei Digital Power Technologies Co Ltd
Publication of EP4702597A1 publication Critical patent/EP4702597A1/fr
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/611—Insulating or insulated package substrates; Interposers; Redistribution layers for connecting multiple chips together
    • H10W70/614—Insulating or insulated package substrates; Interposers; Redistribution layers for connecting multiple chips together the multiple chips being integrally enclosed
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/01—Manufacture or treatment
    • H10W70/05—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/611—Insulating or insulated package substrates; Interposers; Redistribution layers for connecting multiple chips together
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
    • H10W70/68—Shapes or dispositions thereof
    • H10W70/685—Shapes or dispositions thereof comprising multiple insulating layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/401—Package configurations characterised by multiple insulating or insulated package substrates, interposers or RDLs

Landscapes

  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

L'invention concerne un boîtier ou un pré-boîtier (100a, 100b) comprenant : une puce semi-conductrice (140) et deux feuilles de liaison de contact (200, 300) encapsulant la puce semi-conductrice (140). Les deux feuilles de liaison de contact (200, 300) sont liées l'une à l'autre. Chaque feuille de liaison de contact comprend une couche centrale (210, 310) et une couche de liaison (220, 320). La couche centrale comprend une couche isolante centrale (110a, 130a) et une ou plusieurs connexions traversantes métalliques (110b, 110c, 130b) pénétrant dans la couche isolante centrale (110a, 130a). La couche de liaison comprend une couche de liaison isolante (120a, 120b) formée sur la couche isolante centrale (110a, 130a) et une couche de liaison métallique (120g, 120c, 120d) formée sur la ou les connexions traversantes métalliques (110b, 110c, 130b). Les couches de liaison métallique sont conçues pour connecter électriquement et thermiquement la puce semi-conductrice. Les couches de liaison isolantes sont liées les unes aux autres pour former une couche isolante homogène encapsulant la puce semi-conductrice.
EP23735996.3A 2023-06-23 2023-06-23 Structure d'encapsulation de niveau de panneau à interconnexions entièrement parallèles Pending EP4702597A1 (fr)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/EP2023/067106 WO2024260566A1 (fr) 2023-06-23 2023-06-23 Structure d'encapsulation de niveau de panneau à interconnexions entièrement parallèles

Publications (1)

Publication Number Publication Date
EP4702597A1 true EP4702597A1 (fr) 2026-03-04

Family

ID=87067099

Family Applications (1)

Application Number Title Priority Date Filing Date
EP23735996.3A Pending EP4702597A1 (fr) 2023-06-23 2023-06-23 Structure d'encapsulation de niveau de panneau à interconnexions entièrement parallèles

Country Status (3)

Country Link
EP (1) EP4702597A1 (fr)
CN (1) CN121400148A (fr)
WO (1) WO2024260566A1 (fr)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN120497147A (zh) * 2025-04-07 2025-08-15 江苏金脉电控科技有限公司 一种嵌入式功率器件单管封装方法

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10319607B2 (en) * 2014-08-22 2019-06-11 Taiwan Semiconductor Manufacturing Company, Ltd. Package-on-package structure with organic interposer
US11322447B2 (en) * 2019-08-16 2022-05-03 Taiwan Semiconductor Manufacturing Company, Ltd. Dual-sided routing in 3D SiP structure

Also Published As

Publication number Publication date
CN121400148A (zh) 2026-01-23
WO2024260566A1 (fr) 2024-12-26

Similar Documents

Publication Publication Date Title
US9978720B2 (en) Insulated die
US11605609B2 (en) Ultra-thin embedded semiconductor device package and method of manufacturing thereof
US12027481B2 (en) Device including semiconductor chips and method for producing such device
US9437516B2 (en) Chip-embedded packages with backside die connection
CN103367321B (zh) 芯片装置及形成芯片装置的方法
CN103579188B (zh) 嵌入式集成电路封装及其制造方法
US20130043571A1 (en) Power overlay structure with leadframe connections
US8980687B2 (en) Semiconductor device and method of manufacturing thereof
US20150028448A1 (en) Chip Package with Embedded Passive Component
US11908760B2 (en) Package with encapsulated electronic component between laminate and thermally conductive carrier
US20090243079A1 (en) Semiconductor device package
US10763244B2 (en) Power module having power device connected between heat sink and drive unit
CN104170082A (zh) 系统级封装件及其制造方法
CN114005812B (zh) 一种扇出型封装结构及其构造方法
CN106571347A (zh) 绝缘管芯
WO2024260566A1 (fr) Structure d'encapsulation de niveau de panneau à interconnexions entièrement parallèles
CN100592513C (zh) 芯片组件和制造芯片组件的方法
US20230245944A1 (en) Fan-out type package preparation method of fan-out type package
WO2024078682A1 (fr) Substrat d'accumulation pour bloc d'alimentation
US20040089930A1 (en) Simplified stacked chip assemblies
US20240112978A1 (en) Electronic package
US12125824B2 (en) Semiconductor stack structure and manufacturing method thereof
US20250218914A1 (en) Package with component-carrying intermediate structure and additional carrier having reference potential structure
JP4439339B2 (ja) 半導体装置およびその製造方法
JP5271402B2 (ja) 半導体装置の製造方法

Legal Events

Date Code Title Description
STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: UNKNOWN

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: THE INTERNATIONAL PUBLICATION HAS BEEN MADE

PUAI Public reference made under article 153(3) epc to a published international application that has entered the european phase

Free format text: ORIGINAL CODE: 0009012

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: REQUEST FOR EXAMINATION WAS MADE

17P Request for examination filed

Effective date: 20251127

AK Designated contracting states

Kind code of ref document: A1

Designated state(s): AL AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HR HU IE IS IT LI LT LU LV MC ME MK MT NL NO PL PT RO RS SE SI SK SM TR