ES2006602A6 - Sistema de comunicacion asincrono por division en el tiempo. - Google Patents

Sistema de comunicacion asincrono por division en el tiempo.

Info

Publication number
ES2006602A6
ES2006602A6 ES8800843A ES8800843A ES2006602A6 ES 2006602 A6 ES2006602 A6 ES 2006602A6 ES 8800843 A ES8800843 A ES 8800843A ES 8800843 A ES8800843 A ES 8800843A ES 2006602 A6 ES2006602 A6 ES 2006602A6
Authority
ES
Spain
Prior art keywords
communication system
time division
receive
circuit
send
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
ES8800843A
Other languages
English (en)
Inventor
Prycker Martin Louis F De
Mark Lucien M Ryckebusch
Peter Irma A Barri
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nokia Spain SA
Original Assignee
Alcatel Standard Electrics SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Alcatel Standard Electrics SA filed Critical Alcatel Standard Electrics SA
Publication of ES2006602A6 publication Critical patent/ES2006602A6/es
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/02—Details
    • H04J3/06—Synchronising arrangements
    • H04J3/062—Synchronisation of signals having the same nominal but fluctuating bit rates, e.g. using buffers
    • H04J3/0632—Synchronisation of packets and cells, e.g. transmission of voice via a packet network, circuit emulation service [CES]
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F5/00—Methods or arrangements for data conversion without changing the order or content of the data handled
    • G06F5/06—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/54—Store-and-forward switching systems 
    • H04L12/56—Packet switching systems
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2205/00—Indexing scheme relating to group G06F5/00; Methods or arrangements for data conversion without changing the order or content of the data handled
    • G06F2205/06—Indexing scheme relating to groups G06F5/06 - G06F5/16
    • G06F2205/061—Adapt frequency, i.e. clock frequency at one side is adapted to clock frequency, or average clock frequency, at the other side; Not pulse stuffing only
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/04—Speed or phase control by synchronisation signals
    • H04L7/10—Arrangements for initial synchronisation

Landscapes

  • Engineering & Computer Science (AREA)
  • Signal Processing (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Multimedia (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
  • Time-Division Multiplex Systems (AREA)
  • Use Of Switch Circuits For Exchanges And Methods Of Control Of Multiplex Exchanges (AREA)
  • Communication Control (AREA)

Abstract

SISTEMA DE COMUNICACION ASINCRONO POR DIVISION EN EL TIEMPO. SISTEMA DE COMUNICACION ASINCRONO POR DIVISION EN EL TIEMPO, EN EL QUE LAS ESTACIONES DE USUARIO (US1/2) CADA UNA CON UN CIRCUITO EMISOR Y RECEPTOR (SEND1/2, REC1/2) ASOCIADOS, ESTAN ACOPLADAS A UNA RED DE CONMUTACION DE PAQUETES (PSN). CADA CIRCUITO EMISOR INCLUYE UN RELOJ DE EMISION (OSC) Y CADA CIRCUITO RECEPTOR ESTA PROVISTO DE UN RELOJ DE RECEPCION (POSC), QUE CONTROLA LA LECTURA DE UN CIRCUITO DE ALMACENAMIENTO DE PAQUETES (PFIFO), Y DE UN ORDENADOR (COMP) QUE REGULA EL RELOJ DE RECEPCION (POSC) DE TAL FORMA QUE EL NIVEL DE LLENADO DEL CIRCUITO DE ALMACENAMIENTO PERMANECE SUSTANCIALMENTE CONSTANTE.
ES8800843A 1987-03-18 1988-03-18 Sistema de comunicacion asincrono por division en el tiempo. Expired ES2006602A6 (es)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
BE8700282A BE1000415A7 (nl) 1987-03-18 1987-03-18 Asynchroon op basis van tijdsverdeling werkend communicatiesysteem.

Publications (1)

Publication Number Publication Date
ES2006602A6 true ES2006602A6 (es) 1989-05-01

Family

ID=3882577

Family Applications (1)

Application Number Title Priority Date Filing Date
ES8800843A Expired ES2006602A6 (es) 1987-03-18 1988-03-18 Sistema de comunicacion asincrono por division en el tiempo.

Country Status (10)

Country Link
US (1) US5027351A (es)
EP (1) EP0365526B1 (es)
JP (1) JPH02502776A (es)
AT (1) ATE81741T1 (es)
AU (1) AU607475B2 (es)
BE (1) BE1000415A7 (es)
DE (1) DE3875484T2 (es)
ES (1) ES2006602A6 (es)
FI (1) FI96470C (es)
WO (1) WO1988007297A1 (es)

Families Citing this family (33)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3842694A1 (de) * 1988-12-19 1990-06-21 Standard Elektrik Lorenz Ag Demultiplexer mit schaltung zur verringerung des wartezeitjitters
US5317570A (en) * 1990-07-16 1994-05-31 Kabushiki Kaisha Toshiba System and method for learning transmission band of multiplex packet
KR100236506B1 (ko) * 1990-11-29 2000-01-15 퍼킨-엘머시터스인스트루먼츠 폴리머라제 연쇄 반응 수행 장치
US5214691A (en) * 1991-09-26 1993-05-25 Ipc Information Systems, Inc. Key telephone system with virtual private lines
US5237571A (en) * 1991-09-26 1993-08-17 Ipc Information Systems, Inc. Broadcast system for distributed switching network
US5623489A (en) * 1991-09-26 1997-04-22 Ipc Information Systems, Inc. Channel allocation system for distributed digital switching network
US5255264A (en) * 1991-09-26 1993-10-19 Ipc Information Systems, Inc. Distributed control switching network for multi-line telephone communications
US5577075A (en) * 1991-09-26 1996-11-19 Ipc Information Systems, Inc. Distributed clocking system
US5379280A (en) * 1991-09-26 1995-01-03 Ipc Information Systems, Inc. Conferencing system for distributed switching network
FR2682244B1 (fr) * 1991-10-04 1995-01-13 Cit Alcatel Dispositif de synchronisation pour equipement d'extremite d'un reseau de telecommunications numerique a transfert en mode asynchrone.
EP0645914A1 (en) * 1993-09-20 1995-03-29 ALCATEL BELL Naamloze Vennootschap Telecommunication network node
SE515201C2 (sv) * 1993-11-26 2001-06-25 Ericsson Telefon Ab L M Förfarande och anordning för klocksignalgenerering
IT1265424B1 (it) * 1993-12-22 1996-11-22 Alcatel Italia Metodo e disposizione ciruitale di realizzazione della funzione di hpa negli apparati sdh
GB9410943D0 (en) * 1994-06-01 1994-07-20 Newbridge Networks Corp Clock recovery unit
NL9401696A (nl) * 1994-10-14 1996-05-01 Nederland Ptt Bufferuitleesbesturing van ATM ontvanger.
DE19511332A1 (de) * 1995-03-28 1996-10-02 Sel Alcatel Ag Breitbandverteilsystem und Verfahren dazu
JPH11502394A (ja) * 1996-01-12 1999-02-23 フィリップス、エレクトロニクス、ネムローゼ、フェンノートシャップ 広帯域デジタル情報信号を送信するための送信機とその方法、及び受信機
GB9606084D0 (en) * 1996-03-22 1996-05-22 D2B Systems Co Ltd Data frame buffering
US5761203A (en) * 1996-04-04 1998-06-02 Lucent Technologies Inc. Synchronous and asynchronous recovery of signals in an ATM network
FR2761494B1 (fr) * 1997-03-28 1999-12-03 Thomson Multimedia Sa Interface de regulation de debit pour l'enregistrement et/ou la lecture de donnees numeriques
EP0876016B1 (en) * 1997-05-02 2006-03-22 Lsi Logic Corporation Adaptive digital clock recovery
US6876678B1 (en) 1999-02-04 2005-04-05 Cisco Technology, Inc. Time division multiplexing method and apparatus for asynchronous data stream
JP2001016256A (ja) * 1999-06-29 2001-01-19 Fujitsu Ltd インターネットテレフォニーシステム
DE19937245A1 (de) * 1999-08-06 2001-02-15 Siemens Ag Synchronisierungsverfahren und -system für Taktquellen bei insbesondere paketvermittelnden Kommunikationssystemen
AUPQ896300A0 (en) * 2000-07-24 2000-08-17 Nec Australia Pty Ltd A clock synchronisation method for usb sink devices
US7684413B2 (en) * 2002-10-09 2010-03-23 Juniper Networks, Inc. System and method for rate agile adaptive clocking in a packet-based network
CN1830224A (zh) * 2003-08-05 2006-09-06 皇家飞利浦电子股份有限公司 缓冲器管理系统、数字音频接收器、耳机、扬声器、缓冲器管理的方法
CN101873266B (zh) * 2004-08-30 2015-11-25 高通股份有限公司 用于语音ip传输的自适应去抖动缓冲器
US8085678B2 (en) 2004-10-13 2011-12-27 Qualcomm Incorporated Media (voice) playback (de-jitter) buffer adjustments based on air interface
US8155965B2 (en) 2005-03-11 2012-04-10 Qualcomm Incorporated Time warping frames inside the vocoder by modifying the residual
US8355907B2 (en) 2005-03-11 2013-01-15 Qualcomm Incorporated Method and apparatus for phase matching frames in vocoders
US8208500B2 (en) * 2009-12-30 2012-06-26 Nxp B.V. Low-jitter end-to-end latency control scheme for isochronous communications based on transmitter timestamp information
CN106792148A (zh) * 2016-12-09 2017-05-31 广东威创视讯科技股份有限公司 一种提高图像流畅度的方法及系统

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS55127745A (en) * 1979-03-26 1980-10-02 Hitachi Denshi Ltd Bit buffer system
FR2482806A1 (fr) * 1980-05-19 1981-11-20 France Etat Procede et dispositif de synchronisation de signal numerique
FR2538976A1 (fr) * 1982-12-29 1984-07-06 Servel Michel Systeme de commutation de paquets synchrones de longueur fixe
US4569042A (en) * 1983-12-23 1986-02-04 At&T Bell Laboratories Time measurements in a transmission path
FR2579047B1 (fr) * 1985-03-15 1992-04-30 Cochennec Jean Yves Procede de synchronisation par rattrapage de frequence et dispositif de mise en oeuvre du procede
BE903261A (nl) * 1985-09-19 1986-03-19 Bell Telephone Mfg Data communicatiesysteem
EP0215526B1 (en) * 1985-09-19 1991-05-08 BELL TELEPHONE MANUFACTURING COMPANY Naamloze Vennootschap Data communication system
BE1000414A7 (nl) * 1987-03-18 1988-11-22 Bell Telephone Mfg Asynchroon op basis van tijdsverdeling werkend communicatiesysteem.
NL8801120A (nl) * 1988-04-29 1989-11-16 At & T & Philips Telecomm Kruispuntschakelaar voor het doorschakelen van pakketten.

Also Published As

Publication number Publication date
FI894275A0 (fi) 1989-09-11
AU607475B2 (en) 1991-03-07
EP0365526B1 (en) 1992-10-21
JPH02502776A (ja) 1990-08-30
FI96470B (fi) 1996-03-15
FI96470C (fi) 1996-06-25
EP0365526A1 (en) 1990-05-02
DE3875484T2 (de) 1993-04-15
US5027351A (en) 1991-06-25
DE3875484D1 (de) 1992-11-26
WO1988007297A1 (en) 1988-09-22
BE1000415A7 (nl) 1988-11-22
AU1395288A (en) 1988-10-10
ATE81741T1 (de) 1992-11-15

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Legal Events

Date Code Title Description
FD1A Patent lapsed

Effective date: 20080319