ES2010412A6 - Una placa de circuito impreso y metodo para formarla. - Google Patents

Una placa de circuito impreso y metodo para formarla.

Info

Publication number
ES2010412A6
ES2010412A6 ES8900604A ES8900604A ES2010412A6 ES 2010412 A6 ES2010412 A6 ES 2010412A6 ES 8900604 A ES8900604 A ES 8900604A ES 8900604 A ES8900604 A ES 8900604A ES 2010412 A6 ES2010412 A6 ES 2010412A6
Authority
ES
Spain
Prior art keywords
wiring board
printed wiring
chip carrier
forgivable
thermal expansion
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
ES8900604A
Other languages
English (en)
Inventor
Ching-Ping Lo
Kwang Yeh
Manuel B Valle
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Raytheon Co
Original Assignee
Hughes Aircraft Co
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US07/171,047 external-priority patent/US4847136A/en
Priority claimed from US07/171,048 external-priority patent/US4847146A/en
Application filed by Hughes Aircraft Co filed Critical Hughes Aircraft Co
Publication of ES2010412A6 publication Critical patent/ES2010412A6/es
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0271—Arrangements for reducing stress or warp in rigid printed circuit boards, e.g. caused by loads, vibrations or differences in thermal expansion
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B32—LAYERED PRODUCTS
    • B32B—LAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT OR NON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM
    • B32B7/00—Layered products characterised by the relation between layers; Layered products characterised by the relative orientation of features between layers, or by the relative values of a measurable parameter between layers, i.e. products comprising layers having different physical, chemical or physicochemical properties; Layered products characterised by the interconnection of layers
    • B32B7/02—Physical, chemical or physicochemical properties
    • B32B7/027—Thermal properties
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4611—Manufacturing multilayer circuits by laminating two or more circuit boards
    • H05K3/4623—Manufacturing multilayer circuits by laminating two or more circuit boards the circuit boards having internal via connections between two or more circuit layers before lamination, e.g. double-sided circuit boards
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/11—Printed elements for providing electric connections to or between printed circuits
    • H05K1/118—Printed elements for providing electric connections to or between printed circuits specially for flexible printed circuits, e.g. using folded portions
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/01—Dielectrics
    • H05K2201/0104—Properties and characteristics in general
    • H05K2201/0133—Elastomeric or compliant polymer
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/01—Dielectrics
    • H05K2201/0137—Materials
    • H05K2201/015—Fluoropolymer, e.g. polytetrafluoroethylene [PTFE]
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/01—Dielectrics
    • H05K2201/0137—Materials
    • H05K2201/0154—Polyimide
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/06—Thermal details
    • H05K2201/068—Thermal details wherein the coefficient of thermal expansion is important
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09009—Substrate related
    • H05K2201/09109—Locally detached layers, e.g. in multilayer
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/095—Conductive through-holes or vias
    • H05K2201/09536—Buried plated through-holes, i.e. plated through-holes formed in a core before lamination
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10621—Components characterised by their electrical contacts
    • H05K2201/10727—Leadless chip carrier [LCC], e.g. chip-modules for cards
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/0058—Laminating printed circuit boards onto other substrates, e.g. metallic substrates
    • H05K3/0061—Laminating printed circuit boards onto other substrates, e.g. metallic substrates onto a metallic substrate, e.g. a heat sink
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistors
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistors electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistors electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341—Surface mounted components
    • H05K3/3431—Leadless components
    • H05K3/3442—Leadless components having edge contacts, e.g. leadless chip capacitors, chip carriers

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Thermal Sciences (AREA)
  • Manufacturing & Machinery (AREA)
  • Laminated Bodies (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
  • Electric Connection Of Electric Components To Printed Circuits (AREA)

Abstract

UNA PLACA DE CIRCUITO IMPRESO Y METODO PARA FORMARLA. LA PLACA HA SIDO MODIFICADA PARA REDUCIR EL AGRIETAMIENTO DE UNIONES SOLDADAS EMPLEADAS PARA UNIR SOPORTES CERAMICOS SIN CONDUCTORES PARA PASTILLAS DE CIRCUITO IMPRESO. UNA CAPA DE DILATACION RELATIVAMENTE DELGADA SE DISPONE SOBRE LA PARTE SUPERIOR DE LA PLACA DE CIRCUITO IMPRESO USUAL. ESTA CAPA DE DILATACION SE UNE A LA PLACA DE CIRCUITO IMPRESO EXCEPTO EN ZONAS SITUADAS DEBAJO DE LA HUELLA FORMADA POR EL SOPORTE DE PASTILLA Y LAS UNIONES SOLDADAS. EN UNA REALIZACION ALTERNATIVA, LA FALTA DE UNION DEBAJO DE LA HUELLA DEL SOPORTE DE PASTILLA SE DEBE A LA PRESENCIA DE UNA DELGADA CAPA DE POLITETRAFLUOROETILENO (PTFE). SE DESCRIBEN METODOS PARA APLICAR LA CAPA DE PTFE. APLICACION A LA FABRICACION DE CIRCUITOS IMPRESOS.
ES8900604A 1988-03-21 1989-02-20 Una placa de circuito impreso y metodo para formarla. Expired ES2010412A6 (es)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US07/171,047 US4847136A (en) 1988-03-21 1988-03-21 Thermal expansion mismatch forgivable printed wiring board for ceramic leadless chip carrier
US07/171,048 US4847146A (en) 1988-03-21 1988-03-21 Process for fabricating compliant layer board with selectively isolated solder pads

Publications (1)

Publication Number Publication Date
ES2010412A6 true ES2010412A6 (es) 1989-11-01

Family

ID=26866684

Family Applications (1)

Application Number Title Priority Date Filing Date
ES8900604A Expired ES2010412A6 (es) 1988-03-21 1989-02-20 Una placa de circuito impreso y metodo para formarla.

Country Status (7)

Country Link
EP (1) EP0364551B1 (es)
JP (1) JPH02504450A (es)
DE (1) DE3889728T2 (es)
DK (1) DK582089A (es)
ES (1) ES2010412A6 (es)
IL (1) IL88807A (es)
WO (1) WO1989009534A1 (es)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
ES2085231A1 (es) * 1993-12-27 1996-05-16 Arimany Jaime Serrat Util para la practica de un deporte de competicion

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE4129514A1 (de) * 1991-09-05 1993-03-11 Telefunken Electronic Gmbh Gedruckte schaltung mit oberflaechenmontierter steckerleiste
DE59300824D1 (de) * 1992-12-23 1995-11-30 Rheinmetall Ind Gmbh Spannungsfeste Elektronik-Baugruppe.
US6299053B1 (en) 1998-08-19 2001-10-09 Kulicke & Soffa Holdings, Inc. Isolated flip chip or BGA to minimize interconnect stress due to thermal mismatch
JP2001274556A (ja) * 2000-03-23 2001-10-05 Nec Corp プリント配線板

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2486755A1 (fr) * 1980-07-11 1982-01-15 Socapex Support de composants electroniques pour circuits hybrides de grandes dimensions
DE3138987C2 (de) * 1981-09-30 1984-03-29 Siemens AG, 1000 Berlin und 8000 München Einrichtung zum Verhindern von Beschädigungen von Bausteinen bzw. Leiterbahnen auf einer Leiterplatte

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
ES2085231A1 (es) * 1993-12-27 1996-05-16 Arimany Jaime Serrat Util para la practica de un deporte de competicion

Also Published As

Publication number Publication date
EP0364551B1 (en) 1994-05-25
IL88807A (en) 1992-08-18
DK582089D0 (da) 1989-11-20
DE3889728D1 (de) 1994-06-30
DK582089A (da) 1990-01-09
IL88807A0 (en) 1989-07-31
WO1989009534A1 (en) 1989-10-05
EP0364551A1 (en) 1990-04-25
JPH02504450A (ja) 1990-12-13
DE3889728T2 (de) 1994-11-17

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Legal Events

Date Code Title Description
FD1A Patent lapsed

Effective date: 19980401