ES2014382A6 - Empaquetado resistente a la aceleracion para circuitos integrados y procedimiento para su fabricacion. - Google Patents

Empaquetado resistente a la aceleracion para circuitos integrados y procedimiento para su fabricacion.

Info

Publication number
ES2014382A6
ES2014382A6 ES8902892A ES8902892A ES2014382A6 ES 2014382 A6 ES2014382 A6 ES 2014382A6 ES 8902892 A ES8902892 A ES 8902892A ES 8902892 A ES8902892 A ES 8902892A ES 2014382 A6 ES2014382 A6 ES 2014382A6
Authority
ES
Spain
Prior art keywords
integrated circuits
procedure
manufacture
resistant packaging
acceleration resistant
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
ES8902892A
Other languages
English (en)
Inventor
Hans-Peter Opitz
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Rheinmetall Industrie AG
Original Assignee
Rheinmetall GmbH
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Rheinmetall GmbH filed Critical Rheinmetall GmbH
Publication of ES2014382A6 publication Critical patent/ES2014382A6/es
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/20—Configurations of stacked chips
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/754—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked insulating package substrate, interposer or RDL

Landscapes

  • Packaging Frangible Articles (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Non-Metallic Protective Coatings For Printed Circuits (AREA)
  • Buffer Packaging (AREA)

Abstract

EMPAQUETADO RESISTENTE A LA ACELERACION PARA CIRCUITOS INTEGRADOS Y PROCEDIMIENTO PARA SU FABRICACION. SE REFIERE EL INVENTO A UN EMPAQUETADO RESISTENTE A LA ACELERACION PARA CIRCUITOS INTEGRADOS. LOS CIRCUITOS INTEGRADOS USUALMENTE SE EMPAQUETAN EN CAJAS DE PLASTICO O DE CERAMICA. LOS CIRCUITOS EMPAQUETADOS DE TAL MODO, SIN EMBARGO, NO SON UTILIZABLES EN PROYECTILES POR RAZON DE LAS ALTAS ACELERACIONES, QUE SE MANIFIESTAN. POR LO TANTO, EL INVENTO PROPONE DISPONER LOS CIRCUITOS INTEGRADOS (5, 6), EN CADA CASO, ENTRE DOS HOJAS (1, 2) Y FIJARLOS PERIFERICAMENTE EN UN MARCO TENSOR (3, 4).
ES8902892A 1988-11-10 1989-08-18 Empaquetado resistente a la aceleracion para circuitos integrados y procedimiento para su fabricacion. Expired - Lifetime ES2014382A6 (es)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
DE3838085A DE3838085A1 (de) 1988-11-10 1988-11-10 Beschleunigungsfeste verpackung fuer integrierte schaltungen und verfahren zu ihrer herstellung

Publications (1)

Publication Number Publication Date
ES2014382A6 true ES2014382A6 (es) 1990-07-01

Family

ID=6366851

Family Applications (1)

Application Number Title Priority Date Filing Date
ES8902892A Expired - Lifetime ES2014382A6 (es) 1988-11-10 1989-08-18 Empaquetado resistente a la aceleracion para circuitos integrados y procedimiento para su fabricacion.

Country Status (9)

Country Link
US (1) US5160999A (es)
EP (1) EP0396641B1 (es)
JP (1) JPH03502267A (es)
DE (2) DE3838085A1 (es)
DK (1) DK14190A (es)
ES (1) ES2014382A6 (es)
GR (1) GR890100475A (es)
PT (1) PT92267B (es)
WO (1) WO1990005379A1 (es)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5130783A (en) * 1991-03-04 1992-07-14 Texas Instruments Incorporated Flexible film semiconductor package
JP3061954B2 (ja) * 1991-08-20 2000-07-10 株式会社東芝 半導体装置
DE59300824D1 (de) * 1992-12-23 1995-11-30 Rheinmetall Ind Gmbh Spannungsfeste Elektronik-Baugruppe.
US5566078A (en) * 1993-05-26 1996-10-15 Lsi Logic Corporation Integrated circuit cell placement using optimization-driven clustering
US5469366A (en) * 1993-09-20 1995-11-21 Lsi Logic Corporation Method and apparatus for determining the performance of nets of an integrated circuit design on a semiconductor design automation system
US5508558A (en) * 1993-10-28 1996-04-16 Digital Equipment Corporation High density, high speed, semiconductor interconnect using-multilayer flexible substrate with unsupported central portion
JP4015190B2 (ja) * 1995-02-02 2007-11-28 パック テック−パッケージング テクノロジーズ ゲーエムベーハー チップハウジング及びチップハウジングの製造方法
JP3954177B2 (ja) * 1997-01-29 2007-08-08 日本碍子株式会社 金属部材とセラミックス部材との接合構造およびその製造方法
DE19801312A1 (de) 1998-01-15 1999-07-22 Siemens Ag Halbleiterbauelement mit mehreren Substratlagen und zumindest einem Halbleiterchip und einem Verfahren zum Herstellen eines solchen Halbleiterbauelementes
DE19808986A1 (de) 1998-03-03 1999-09-09 Siemens Ag Halbleiterbauelement mit mehreren Halbleiterchips

Family Cites Families (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3221286A (en) * 1961-07-31 1965-11-30 Sperry Rand Corp Connector for printed circuit strip transmission line
US3152288A (en) * 1962-04-06 1964-10-06 Mittler Sheldon Circuit assembly
US3376479A (en) * 1965-04-30 1968-04-02 Sperry Rand Corp Means for operatively connecting printed circuit boards
US3772776A (en) * 1969-12-03 1973-11-20 Thomas & Betts Corp Method of interconnecting memory plane boards
US3716846A (en) * 1970-01-24 1973-02-13 R Hafner Connector sheet with contacts on opposite sides
US3766439A (en) * 1972-01-12 1973-10-16 Gen Electric Electronic module using flexible printed circuit board with heat sink means
US4026011A (en) * 1975-08-28 1977-05-31 Burroughs Corporation Flexible circuit assembly
US3971127A (en) * 1975-09-10 1976-07-27 Bell Telephone Laboratories, Incorporated Method of fabricating a printed wiring board assembly
US4203127A (en) * 1977-07-18 1980-05-13 Motorola, Inc. Package and method of packaging semiconductor wafers
US4412272A (en) * 1981-08-31 1983-10-25 General Dynamics, Pomona Division Flexible printed circuit card assembly
US4504850A (en) * 1981-10-02 1985-03-12 Westinghouse Electric Corp. Disc-type semiconductor mounting arrangement with force distribution spacer
JPS59172253A (ja) * 1983-03-18 1984-09-28 Mitsubishi Electric Corp 半導体装置
JPS6127633A (ja) * 1984-07-17 1986-02-07 Nec Corp プラズマエツチング装置
JPS6127663A (ja) * 1984-07-17 1986-02-07 Nec Corp 半導体集積回路
US4766670A (en) * 1987-02-02 1988-08-30 International Business Machines Corporation Full panel electronic packaging structure and method of making same
US4841355A (en) * 1988-02-10 1989-06-20 Amdahl Corporation Three-dimensional microelectronic package for semiconductor chips
JPH06127663A (ja) * 1992-10-21 1994-05-10 Nippon Steel Corp ベルトコンベア上の粉粒塊状物の積載状態の測定方法及びコンベア蛇行制御方法

Also Published As

Publication number Publication date
GR890100475A (el) 1991-12-30
DK14190D0 (da) 1990-01-17
DE58908413D1 (de) 1994-10-27
JPH03502267A (ja) 1991-05-23
EP0396641A1 (de) 1990-11-14
DK14190A (da) 1990-05-17
PT92267B (pt) 1995-09-12
PT92267A (pt) 1990-05-31
DE3838085A1 (de) 1990-05-17
US5160999A (en) 1992-11-03
EP0396641B1 (de) 1994-09-21
WO1990005379A1 (de) 1990-05-17

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Legal Events

Date Code Title Description
FD1A Patent lapsed

Effective date: 20001102