ES2033286T3 - Circuito para el procesamiento de senales digitales. - Google Patents

Circuito para el procesamiento de senales digitales.

Info

Publication number
ES2033286T3
ES2033286T3 ES198787116701T ES87116701T ES2033286T3 ES 2033286 T3 ES2033286 T3 ES 2033286T3 ES 198787116701 T ES198787116701 T ES 198787116701T ES 87116701 T ES87116701 T ES 87116701T ES 2033286 T3 ES2033286 T3 ES 2033286T3
Authority
ES
Spain
Prior art keywords
digital signal
signal processing
processing circuit
digital
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
ES198787116701T
Other languages
English (en)
Inventor
Werner Dipl.-Ing. Scholz
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Deutsche Thomson Brandt GmbH
Original Assignee
Deutsche Thomson Brandt GmbH
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Deutsche Thomson Brandt GmbH filed Critical Deutsche Thomson Brandt GmbH
Application granted granted Critical
Publication of ES2033286T3 publication Critical patent/ES2033286T3/es
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/04—Speed or phase control by synchronisation signals
    • H04L7/08—Speed or phase control by synchronisation signals the synchronisation signals recurring cyclically
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
    • G11B20/00—Signal processing not specific to the method of recording or reproducing; Circuits therefor
    • G11B20/10—Digital recording or reproducing
    • G11B20/10009—Improvement or modification of read or write signals
    • G11B20/10222—Improvement or modification of read or write signals clock-related aspects, e.g. phase or frequency adjustment or bit synchronisation
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
    • G11B20/00—Signal processing not specific to the method of recording or reproducing; Circuits therefor
    • G11B20/10—Digital recording or reproducing
    • G11B20/10009—Improvement or modification of read or write signals
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
    • G11B20/00—Signal processing not specific to the method of recording or reproducing; Circuits therefor
    • G11B20/10—Digital recording or reproducing
    • G11B20/14—Digital recording or reproducing using self-clocking codes
    • G11B20/1403—Digital recording or reproducing using self-clocking codes characterised by the use of two levels

Landscapes

  • Engineering & Computer Science (AREA)
  • Signal Processing (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing For Digital Recording And Reproducing (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
  • Mobile Radio Communication Systems (AREA)
  • Communication Control (AREA)

Abstract

INTERRUPTOR PARA LA ELABORACION DE SEÑALES DIGITALES, EN EL QUE SE REGENERA UNA SEÑAL DE TACTO C DE LA SEÑAL DE ENTRADA DIGITAL. POR EL INVENTO SE CREA UN RECONOCIMIENTO MAS RAPIDO Y SEGURO DE RESULTADOS DE SINCRONIZACION (BIT SLIP) Y CON ELLO UNA POSIBILIDAD PARA EVITAR RAPIDAMENTE PERTURBACIONES. APLICACION POR EJEMPLO EN DISEÑO DE SEÑAL CD O DIGITAL EN BANDAS.
ES198787116701T 1986-11-21 1987-11-12 Circuito para el procesamiento de senales digitales. Expired - Lifetime ES2033286T3 (es)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
DE19863639886 DE3639886A1 (de) 1986-11-21 1986-11-21 Schaltung zur verarbeitung digitaler signale

Publications (1)

Publication Number Publication Date
ES2033286T3 true ES2033286T3 (es) 1993-03-16

Family

ID=6314510

Family Applications (1)

Application Number Title Priority Date Filing Date
ES198787116701T Expired - Lifetime ES2033286T3 (es) 1986-11-21 1987-11-12 Circuito para el procesamiento de senales digitales.

Country Status (7)

Country Link
EP (1) EP0268944B1 (es)
JP (1) JPH07112188B2 (es)
KR (1) KR910001405B1 (es)
AT (1) ATE76997T1 (es)
DE (2) DE3639886A1 (es)
ES (1) ES2033286T3 (es)
GR (1) GR3005261T3 (es)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR910009808B1 (ko) * 1989-06-13 1991-11-30 한국전기통신공사 디지틀 자동 위상 제어 리타이밍 회로
DE3928676A1 (de) * 1989-08-30 1991-03-07 Thomson Brandt Gmbh Schaltung zur erkennung eines nutzsignals in einem binaeren signal
US5410557A (en) * 1989-08-30 1995-04-25 Deutsche Thomson-Brandt Gmbh Method and apparatus for recognizing valid components in a digital signal
DE19707512C1 (de) * 1997-02-25 1998-08-27 Siemens Ag Verfahren und Vorrichtung zum Regenerieren/Substituieren eines Taktpulses auf einen Ausgangspuls

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB1280827A (en) * 1968-10-28 1972-07-05 Post Office Improvements relating to apparatus for synchronizing a clock with a received signal
US4200845A (en) * 1978-12-22 1980-04-29 Sperry Rand Corporation Phase comparator with dual phase detectors
GB2068687A (en) * 1980-01-09 1981-08-12 Decca Ltd Digital synchronising system
JPS5720052A (en) * 1980-07-11 1982-02-02 Toshiba Corp Input data synchronizing circuit
US4373204A (en) * 1981-02-02 1983-02-08 Bell Telephone Laboratories, Incorporated Phase locked loop timing recovery circuit
DE3130482A1 (de) * 1981-07-23 1983-02-10 Robert Bosch Gmbh, 7000 Stuttgart Verfahren zur rueckgewinnung des bei einem datenuebertragunssystem empfangsseitig benoetigten taktes und vorrichtung zur durchfuehrung des verfahrens
DE3151251A1 (de) * 1981-12-24 1983-07-07 Robert Bosch Gmbh, 7000 Stuttgart Verfahren und schaltungsanordnung zur wiedergabe digital codierter signale
JPS5986385A (ja) * 1982-11-09 1984-05-18 Toshiba Corp サンプリングパルス生成回路
US4525754A (en) * 1983-04-06 1985-06-25 Ampex Corporation System and method for synchronization of rotary head magnetic recording/reproducing devices

Also Published As

Publication number Publication date
EP0268944A3 (en) 1989-11-15
KR910001405B1 (ko) 1991-03-04
GR3005261T3 (es) 1993-05-24
ATE76997T1 (de) 1992-06-15
DE3639886A1 (de) 1988-06-01
DE3779573D1 (de) 1992-07-09
EP0268944A2 (de) 1988-06-01
EP0268944B1 (de) 1992-06-03
JPH07112188B2 (ja) 1995-11-29
JPS63138829A (ja) 1988-06-10
KR880006862A (ko) 1988-07-25

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