ES2036453A2 - Estructura de test para la caracterizacion, del latch-up en circuitos cmo5. - Google Patents
Estructura de test para la caracterizacion, del latch-up en circuitos cmo5.Info
- Publication number
- ES2036453A2 ES2036453A2 ES919101476A ES9101476A ES2036453A2 ES 2036453 A2 ES2036453 A2 ES 2036453A2 ES 919101476 A ES919101476 A ES 919101476A ES 9101476 A ES9101476 A ES 9101476A ES 2036453 A2 ES2036453 A2 ES 2036453A2
- Authority
- ES
- Spain
- Prior art keywords
- latch
- cmos
- characterisation
- test structure
- cmos circuits
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000012512 characterization method Methods 0.000 title abstract 2
- 238000005516 engineering process Methods 0.000 abstract 1
- 238000000034 method Methods 0.000 abstract 1
- 238000004377 microelectronic Methods 0.000 abstract 1
- 230000035945 sensitivity Effects 0.000 abstract 1
Landscapes
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Tests Of Electronic Circuits (AREA)
Abstract
LA ESTRUCTURA DE TEST PARA LA CARACTERIZACION DEL LASTCH-UP EN CIRCUITOS CMOS EN UN DISPOSITIVO QUE PERMITE LA DETERMINACION EN LA SENSIBILIDAD DE DISTINTAS GEOMETRIAS Y PROCESOS TECNOLOGICOS AL FENOMENO INDESEADO CONOCIDO POR LATCH-UP. MEDIANTE LA COMBINACION DE UN DISPOSITICO P-N-P-N SENSIBLE, UNA CAPACIDAD CMOS Y UNA RESISTENCIA INTEGRADA SE CONSIGUE IMPLEMENTAR UN OSCILADOR ASTABLE CUYA SEÑAL DE SALIDA PERMITE OBTENER DIRECTAMENTE LOS PARAMETROS CARACTERISTICOS LATCH-UP SIMPLEMENTE VISUALIZANDOLA MEDIANTE UN OSCILOSCOPIO ANALOGICO O DIGITAL. LA ESTRUCTURA PUEDE IMPLEMENTARSE EN CUALQUIER TECNOLOGIA CMOS LSI O VLSI, POR SUPERPOSICION DE UN MINIMO DE NUEVE NIVELES DE MASCARA CON UN DISEÑO TIPICO COMO EL PRESENTADO. LA APLICACION ES DENTRO DEL MUNDO DE LA INDUSTRIA MICROELECTRONICA.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| ES9101476A ES2036453B1 (es) | 1991-06-21 | 1991-06-21 | Estructura de test para la caracterizacion, del latch-up en circuitos cmo5. |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| ES9101476A ES2036453B1 (es) | 1991-06-21 | 1991-06-21 | Estructura de test para la caracterizacion, del latch-up en circuitos cmo5. |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| ES2036453A2 true ES2036453A2 (es) | 1993-05-16 |
| ES2036453R ES2036453R (es) | 1995-05-16 |
| ES2036453B1 ES2036453B1 (es) | 1995-12-16 |
Family
ID=8272762
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| ES9101476A Expired - Fee Related ES2036453B1 (es) | 1991-06-21 | 1991-06-21 | Estructura de test para la caracterizacion, del latch-up en circuitos cmo5. |
Country Status (1)
| Country | Link |
|---|---|
| ES (1) | ES2036453B1 (es) |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0345701A2 (de) * | 1988-06-08 | 1989-12-13 | Siemens Aktiengesellschaft | Verfahren zur Untersuchung der Latch-Up-Ausbreitung in CMOS-Schaltungen |
| EP0345702A2 (de) * | 1988-06-08 | 1989-12-13 | Siemens Aktiengesellschaft | Verfahren zur Untersuchung der Latch-Up-Ausbreitung in CMOS-Schaltungen |
| EP0382865A1 (de) * | 1989-02-14 | 1990-08-22 | Siemens Aktiengesellschaft | Anordnung zur Verminderung von Latch-up-Störanfälligkeit bei CMOS-Halbleiterschaltungen |
-
1991
- 1991-06-21 ES ES9101476A patent/ES2036453B1/es not_active Expired - Fee Related
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0345701A2 (de) * | 1988-06-08 | 1989-12-13 | Siemens Aktiengesellschaft | Verfahren zur Untersuchung der Latch-Up-Ausbreitung in CMOS-Schaltungen |
| EP0345702A2 (de) * | 1988-06-08 | 1989-12-13 | Siemens Aktiengesellschaft | Verfahren zur Untersuchung der Latch-Up-Ausbreitung in CMOS-Schaltungen |
| EP0382865A1 (de) * | 1989-02-14 | 1990-08-22 | Siemens Aktiengesellschaft | Anordnung zur Verminderung von Latch-up-Störanfälligkeit bei CMOS-Halbleiterschaltungen |
Also Published As
| Publication number | Publication date |
|---|---|
| ES2036453B1 (es) | 1995-12-16 |
| ES2036453R (es) | 1995-05-16 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| FD1A | Patent lapsed |
Effective date: 20000707 |