ES2055517T3 - Procedimiento para la reduccion modular de numeros. - Google Patents

Procedimiento para la reduccion modular de numeros.

Info

Publication number
ES2055517T3
ES2055517T3 ES91200523T ES91200523T ES2055517T3 ES 2055517 T3 ES2055517 T3 ES 2055517T3 ES 91200523 T ES91200523 T ES 91200523T ES 91200523 T ES91200523 T ES 91200523T ES 2055517 T3 ES2055517 T3 ES 2055517T3
Authority
ES
Spain
Prior art keywords
modular reduction
exponentiation
modular
accelerated
digit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
ES91200523T
Other languages
English (en)
Inventor
Consta No
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Koninklijke PTT Nederland NV
Original Assignee
Koninklijke PTT Nederland NV
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Koninklijke PTT Nederland NV filed Critical Koninklijke PTT Nederland NV
Application granted granted Critical
Publication of ES2055517T3 publication Critical patent/ES2055517T3/es
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/60—Methods or arrangements for performing computations using a digital non-denominational number representation, i.e. number representation without radix; Computing devices using combinations of denominational and non-denominational quantity representations, e.g. using difunction pulse trains, STEELE computers, phase computers
    • G06F7/72—Methods or arrangements for performing computations using a digital non-denominational number representation, i.e. number representation without radix; Computing devices using combinations of denominational and non-denominational quantity representations, e.g. using difunction pulse trains, STEELE computers, phase computers using residue arithmetic
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L9/00—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols
    • H04L9/30—Public key, i.e. encryption algorithm being computationally infeasible to invert or user's encryption keys not requiring secrecy
    • H04L9/3006—Public key, i.e. encryption algorithm being computationally infeasible to invert or user's encryption keys not requiring secrecy underlying computational problems or public-key parameters
    • H04L9/3013—Public key, i.e. encryption algorithm being computationally infeasible to invert or user's encryption keys not requiring secrecy underlying computational problems or public-key parameters involving the discrete logarithm problem, e.g. ElGamal or Diffie-Hellman systems

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computing Systems (AREA)
  • Physics & Mathematics (AREA)
  • Computational Mathematics (AREA)
  • Mathematical Analysis (AREA)
  • Mathematical Optimization (AREA)
  • Pure & Applied Mathematics (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • General Engineering & Computer Science (AREA)
  • Computer Security & Cryptography (AREA)
  • Mathematical Physics (AREA)
  • Signal Processing (AREA)
  • Electrotherapy Devices (AREA)
  • Complex Calculations (AREA)
  • Storage Device Security (AREA)
  • Coupling Device And Connection With Printed Circuit (AREA)
  • Spinning Or Twisting Of Yarns (AREA)
  • Control By Computers (AREA)
  • Pinball Game Machines (AREA)
  • Two-Way Televisions, Distribution Of Moving Picture Or The Like (AREA)
  • Control Of El Displays (AREA)
  • Mechanical Light Control Or Optical Switches (AREA)
  • Body Structure For Vehicles (AREA)

Abstract

EN TECNICAS CRIPTOGRAFICAS BASADAS EN UN PROBLEMA LOGARITIMICO DISCONTINUO SE UTILIZA GRAN NUMERO DE MODULOS DE EXPONENCIACION. SI, EN ESTE METODO, LA EXPONENCIACION SE REALIZA PRIMERO POR COMPLETO Y LA REDUCCION MODULAR SOLO SE COMPLETA MAS TARDE, PARA ELLO HACE FALTA MUCHO TIEMPO DE COMPUTACION Y UNA GRAN CAPACIDAD DE MEMORIA. ES SABIDO QUE LA EXPONENCIACION PUEDE ACELERARSE MULTIPLICANDO Y ELEVANDO AL CUADRADO REPETITIVAMENTE, CON UNA REDUCCION MODULAR DESPUES DE CADA PASO. LA INVENCION FACILITA UN METODO PARA ACELERAR TAMBIEN LA REDUCCION MODULAR AL MISMO TIEMPO, COMO RESULTADO DEL MAL EL GRAN NUMERO DE MODULO DE EXPONENCIACION PUEDE ADEMAS ACELERARSE. CON ESTE MOTIVO, LA INVENCION DESCRIBE UN PROTOCOLO PARA UNA REDUCCION MODULAR DE UN NUMERO X 2N-DIGITO EN UN SISTEMA NUMERICO CON BASE B PARA OBTENER UN N-DIGITO RESTANTE, EN EL QUE SE UTILIZA UN MODULO ESPECIFICO P QUE SATISFACE P= B (ELEVADO A N) < A < B. EL METODO QUE SIGUE LA INVENCION NO REDUCE LA SEGURIDAD DEL SISTEMA CRIPTOGRAFICOPARA EL QUE SE REALIZA LA EXPONENCIACION MODULAR.
ES91200523T 1990-03-15 1991-03-12 Procedimiento para la reduccion modular de numeros. Expired - Lifetime ES2055517T3 (es)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
NL9000593A NL9000593A (nl) 1990-03-15 1990-03-15 Werkwijze voor het modulair reduceren van getallen.

Publications (1)

Publication Number Publication Date
ES2055517T3 true ES2055517T3 (es) 1994-08-16

Family

ID=19856745

Family Applications (1)

Application Number Title Priority Date Filing Date
ES91200523T Expired - Lifetime ES2055517T3 (es) 1990-03-15 1991-03-12 Procedimiento para la reduccion modular de numeros.

Country Status (8)

Country Link
EP (1) EP0449349B1 (es)
AT (1) ATE105097T1 (es)
DE (1) DE69101800T2 (es)
DK (1) DK0449349T3 (es)
ES (1) ES2055517T3 (es)
FI (1) FI911284A7 (es)
NL (1) NL9000593A (es)
NO (1) NO910949L (es)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6963977B2 (en) * 2000-12-19 2005-11-08 International Business Machines Corporation Circuits and methods for modular exponentiation
US7552164B1 (en) 2008-04-24 2009-06-23 International Business Machines Corporation Accelerated prime sieving using architecture-optimized partial prime product table

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4424414A (en) * 1978-05-01 1984-01-03 Board Of Trustees Of The Leland Stanford Junior University Exponentiation cryptographic apparatus and method
GB8815868D0 (en) * 1988-07-04 1988-08-10 British Aerospace Digital signal processing
EP0381523A3 (en) * 1989-02-02 1993-03-03 Kabushiki Kaisha Toshiba Server-aided computation method and distributed information processing unit

Also Published As

Publication number Publication date
FI911284A0 (fi) 1991-03-15
NO910949D0 (no) 1991-03-11
ATE105097T1 (de) 1994-05-15
DE69101800T2 (de) 1994-09-29
DE69101800D1 (de) 1994-06-01
EP0449349A1 (en) 1991-10-02
NO910949L (no) 1991-09-16
EP0449349B1 (en) 1994-04-27
DK0449349T3 (da) 1994-09-05
NL9000593A (nl) 1991-10-01
FI911284A7 (fi) 1991-09-16

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