ES2074058T3 - Procedimiento para el tratamiento de palabras codificadas binarias supervisables en la paridad, que experimentan en el transcurso de su transmision una atenuacion digital y/o conversion de codigo. - Google Patents

Procedimiento para el tratamiento de palabras codificadas binarias supervisables en la paridad, que experimentan en el transcurso de su transmision una atenuacion digital y/o conversion de codigo.

Info

Publication number
ES2074058T3
ES2074058T3 ES89101434T ES89101434T ES2074058T3 ES 2074058 T3 ES2074058 T3 ES 2074058T3 ES 89101434 T ES89101434 T ES 89101434T ES 89101434 T ES89101434 T ES 89101434T ES 2074058 T3 ES2074058 T3 ES 2074058T3
Authority
ES
Spain
Prior art keywords
parity
code conversion
treatment
supervisable
experience
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
ES89101434T
Other languages
English (en)
Inventor
Gerd Dipl-Ing Bocker
Rostislav Dipl-Ing Kaderka
Rudolf Dipl-Ing Krumenacker
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Siemens AG
Siemens Corp
Original Assignee
Siemens AG
Siemens Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siemens AG, Siemens Corp filed Critical Siemens AG
Application granted granted Critical
Publication of ES2074058T3 publication Critical patent/ES2074058T3/es
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/09—Error detection only, e.g. using cyclic redundancy check [CRC] codes or single parity bit
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/09—Error detection only, e.g. using cyclic redundancy check [CRC] codes or single parity bit
    • H03M13/098—Error detection only, e.g. using cyclic redundancy check [CRC] codes or single parity bit using single parity bit
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/14—Error detection or correction of the data by redundancy in operations

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Probability & Statistics with Applications (AREA)
  • Quality & Reliability (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Error Detection And Correction (AREA)
  • Detection And Prevention Of Errors In Transmission (AREA)
  • Detection And Correction Of Errors (AREA)
  • Dc Digital Transmission (AREA)

Abstract

AL ENCONTRARSE UNA PARIDAD EQUIVOCADA ANTES DE REALIZARA UNA AMORTIGUACION O UNA CONVERSION DE CODIGO, SE INVIERTE EL BIT DE PARIDAD DE LAS PALABRAS CODIFICADAS SUJETAS A ESTE TRATAMIENTO DE FORMA QUE MODIFICACIONES DE POLARIDAD CAUSADAS POR LA AMORTIGUACION O CONVERSION DE CODIGO NO PUEDEN TENER LA CONSECUENCIA QUE NO SE RECONOZCAN ESTAS PARIDADES EQUIVOCADAS.
ES89101434T 1989-01-27 1989-01-27 Procedimiento para el tratamiento de palabras codificadas binarias supervisables en la paridad, que experimentan en el transcurso de su transmision una atenuacion digital y/o conversion de codigo. Expired - Lifetime ES2074058T3 (es)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
EP89101434A EP0379625B1 (de) 1989-01-27 1989-01-27 Verfahren zur Behandlung von paritätsüberwachbaren Binärcodeworten, die im Zuge ihrer Übertragung eine digitale Dämpfung und/oder Codekonvertierung erfahren

Publications (1)

Publication Number Publication Date
ES2074058T3 true ES2074058T3 (es) 1995-09-01

Family

ID=8200912

Family Applications (1)

Application Number Title Priority Date Filing Date
ES89101434T Expired - Lifetime ES2074058T3 (es) 1989-01-27 1989-01-27 Procedimiento para el tratamiento de palabras codificadas binarias supervisables en la paridad, que experimentan en el transcurso de su transmision una atenuacion digital y/o conversion de codigo.

Country Status (6)

Country Link
US (1) US5123019A (es)
EP (1) EP0379625B1 (es)
JP (1) JPH0831807B2 (es)
AT (1) ATE125404T1 (es)
DE (1) DE58909353D1 (es)
ES (1) ES2074058T3 (es)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5285456A (en) * 1991-05-15 1994-02-08 International Business Machines Corporation System and method for improving the integrity of control information
GB2281179B (en) * 1993-08-18 1998-03-11 Roke Manor Research Apparatus for use in equipment providing a digital radio link between a fixed and a mobile radio unit
US5856989A (en) * 1996-08-13 1999-01-05 Hewlett-Packard Company Method and apparatus for parity block generation

Family Cites Families (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4051355A (en) * 1976-04-29 1977-09-27 Ncr Corporation Apparatus and method for increasing the efficiency of random access storage
US4103823A (en) * 1976-12-20 1978-08-01 International Business Machines Corporation Parity checking scheme for detecting word line failure in multiple byte arrays
US4155070A (en) * 1977-12-01 1979-05-15 Northern Telecom Limited Code-converter with preservation of parity
JPS5577260A (en) * 1978-12-05 1980-06-10 Fujitsu Ltd Error detection system of digital communication unit
JPS55105897A (en) * 1979-01-31 1980-08-13 Hitachi Koki Co Ltd Memory device
US4271521A (en) * 1979-07-09 1981-06-02 The Anaconda Company Address parity check system
JPS5713836A (en) * 1980-06-27 1982-01-23 Toshiba Corp Channel synchronization system
US4429391A (en) * 1981-05-04 1984-01-31 Bell Telephone Laboratories, Incorporated Fault and error detection arrangement
JPS5834656A (ja) * 1981-08-25 1983-03-01 Fujitsu Ltd 符号変換方式
US4580265A (en) * 1983-06-30 1986-04-01 International Business Machines Corporation Failure detection method and apparatus
US4730320A (en) * 1985-02-07 1988-03-08 Mitsubishi Denki Kabushiki Kaisha Semiconductor memory device
JPS6262360U (es) * 1985-10-04 1987-04-17
US4700358A (en) * 1985-11-18 1987-10-13 Hayes Microcomputer Products, Inc. Synchronous/asynchronous modem
US4774712A (en) * 1986-10-01 1988-09-27 International Business Machines Corporation Redundant storage device having address determined by parity of lower address bits
JPS63102517A (ja) * 1986-10-20 1988-05-07 Nec Corp 機器障害信号伝送方式
EP0267499B1 (de) * 1986-10-31 1991-07-24 Siemens Nixdorf Informationssysteme Aktiengesellschaft Verfahren zur Paritätsbitermittlung und zur Überwachung der Übertragung beim Datenschieben sowie Schaltungsanordnung zur Durchführung der Verfahren

Also Published As

Publication number Publication date
DE58909353D1 (de) 1995-08-24
EP0379625B1 (de) 1995-07-19
JPH02234517A (ja) 1990-09-17
ATE125404T1 (de) 1995-08-15
EP0379625A1 (de) 1990-08-01
JPH0831807B2 (ja) 1996-03-27
US5123019A (en) 1992-06-16

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