ES2084836T3 - Disposicion de semiconductores integrada monoliticamente. - Google Patents

Disposicion de semiconductores integrada monoliticamente.

Info

Publication number
ES2084836T3
ES2084836T3 ES91919865T ES91919865T ES2084836T3 ES 2084836 T3 ES2084836 T3 ES 2084836T3 ES 91919865 T ES91919865 T ES 91919865T ES 91919865 T ES91919865 T ES 91919865T ES 2084836 T3 ES2084836 T3 ES 2084836T3
Authority
ES
Spain
Prior art keywords
monolithically integrated
integrated semiconductor
electrode
voltage
gifted
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
ES91919865T
Other languages
English (en)
Inventor
Hartmut Michel
Peter Flohrs
Alfred Goerlach
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Robert Bosch GmbH
Original Assignee
Robert Bosch GmbH
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Robert Bosch GmbH filed Critical Robert Bosch GmbH
Application granted granted Critical
Publication of ES2084836T3 publication Critical patent/ES2084836T3/es
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/64—Double-diffused metal-oxide semiconductor [DMOS] FETs
    • H10D30/66—Vertical DMOS [VDMOS] FETs
    • H10D30/668—Vertical DMOS [VDMOS] FETs having trench gate electrodes, e.g. UMOS transistors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/111—Field plates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/60—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D10/00 or H10D18/00, e.g. integration of BJTs
    • H10D84/641—Combinations of only vertical BJTs
    • H10D84/642—Combinations of non-inverted vertical BJTs of the same conductivity type having different characteristics, e.g. Darlington transistors

Landscapes

  • Bipolar Integrated Circuits (AREA)
  • Bipolar Transistors (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

SE PROPONE UN DISPOSITIVO DE SEMICONDUCTORES MONOLITICAMENTE INTEGRADO, EN EL QUE EN LA SUPERFICIE PRINCIPAL DE UN TRANSISTOR NPN O PNP, MONOLITICAMENTE INTEGRADO, SE HA DISPUESTO UN ELECTRODO (D1) PARA LA LIMITACION DE LA TENSION INTERNA, EL CUAL CUBRE UNA UNICA ZONA DE TRANSICION ENTRE UNA ZONA ALTAMENTE DOTADA (5), Y EL SUBSTRATO ESCASAMENTE DOTADO (1). UNA ZONA CONTIGUA ALTAMENTE DOTADA (4) NO ES CUBIERTA POR EL ELECTRODO (D1). POR MEDIO DE LA CONEXION DEL ELECTRODO METALICO (D1) A LA TOMA (12) DE UN DIVISOR DE TENSION (R1,R2), SE PUEDE CONSEGUIR UNA TENSION DE PASO, QUE ES MAYOR QUE LA SUMA DE LA TENSION DE PASO EMPOBRECIDA Y DE LA TENSION DE PASO ENRIQUECIDA.
ES91919865T 1990-12-12 1991-11-19 Disposicion de semiconductores integrada monoliticamente. Expired - Lifetime ES2084836T3 (es)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
DE4039662A DE4039662A1 (de) 1990-12-12 1990-12-12 Monolithisch integrierte halbleiteranordnung

Publications (1)

Publication Number Publication Date
ES2084836T3 true ES2084836T3 (es) 1996-05-16

Family

ID=6420146

Family Applications (1)

Application Number Title Priority Date Filing Date
ES91919865T Expired - Lifetime ES2084836T3 (es) 1990-12-12 1991-11-19 Disposicion de semiconductores integrada monoliticamente.

Country Status (6)

Country Link
US (1) US5449949A (es)
EP (1) EP0561809B1 (es)
JP (1) JP3236290B2 (es)
DE (2) DE4039662A1 (es)
ES (1) ES2084836T3 (es)
WO (1) WO1992010855A1 (es)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE4343140B4 (de) * 1993-12-17 2009-12-03 Robert Bosch Gmbh Halbleiteranordnung zur Beeinflussung der Durchbruchsspannung von Transistoren
DE19526902A1 (de) * 1995-07-22 1997-01-23 Bosch Gmbh Robert Monolithisch integrierte planare Halbleiteranordnung

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3227536A1 (de) * 1982-01-20 1983-07-28 Robert Bosch Gmbh, 7000 Stuttgart Darlington-transistorschaltung
US4916494A (en) * 1984-05-04 1990-04-10 Robert Bosch Gmbh Monolithic integrated planar semiconductor system and process for making the same
DE3417474A1 (de) * 1984-05-11 1985-11-14 Robert Bosch Gmbh, 7000 Stuttgart Monolithisch integrierte planare halbleiteranordnung

Also Published As

Publication number Publication date
DE4039662A1 (de) 1992-06-17
WO1992010855A1 (de) 1992-06-25
JP3236290B2 (ja) 2001-12-10
EP0561809A1 (de) 1993-09-29
DE59107560D1 (de) 1996-04-18
EP0561809B1 (de) 1996-03-13
US5449949A (en) 1995-09-12
JPH06503444A (ja) 1994-04-14

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