ES2087979T3 - Dispositivo de contraste de datos y sistema de transmision numerica de datos resultante. - Google Patents

Dispositivo de contraste de datos y sistema de transmision numerica de datos resultante.

Info

Publication number
ES2087979T3
ES2087979T3 ES91401931T ES91401931T ES2087979T3 ES 2087979 T3 ES2087979 T3 ES 2087979T3 ES 91401931 T ES91401931 T ES 91401931T ES 91401931 T ES91401931 T ES 91401931T ES 2087979 T3 ES2087979 T3 ES 2087979T3
Authority
ES
Spain
Prior art keywords
data
transmission system
data transmission
resulting numerical
numerical data
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
ES91401931T
Other languages
English (en)
Inventor
Roland Marbot
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Bull SAS
Original Assignee
Bull SAS
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Bull SAS filed Critical Bull SAS
Application granted granted Critical
Publication of ES2087979T3 publication Critical patent/ES2087979T3/es
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
    • H04L7/0337—Selecting between two or more discretely delayed clocks or selecting between two or more discretely delayed received code signals
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/04—Speed or phase control by synchronisation signals
    • H04L7/041—Speed or phase control by synchronisation signals using special codes as synchronising signal
    • H04L7/044—Speed or phase control by synchronisation signals using special codes as synchronising signal using a single bit, e.g. start stop bit
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/04—Speed or phase control by synchronisation signals
    • H04L7/048—Speed or phase control by synchronisation signals using the properties of error detecting or error correcting codes, e.g. parity as synchronisation signal

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
  • Time-Division Multiplex Systems (AREA)

Abstract

EL DISPOSITIVO DE MUESTREO DE DATOS RECURRENTES A UN PERIODO R EN UNA SEÑAL DE DATOS (TS) COMPRENDE UN CIRCUITO DE REGLAJE (43) QUE REGULA EL RETARDO DE UNA SEÑAL DE RELOJ RESPECTO DE UN FRENTE DE LA SEÑAL DE DATOS SOBRE UN VALOR (N + (ALFA)) DONDE N ES UN NUMERO ENTERO POSITIVO O NULO Y (ALFA) ES UN NUMERO POSITIVO INFERIOR A 1. LA INVENCION SE APLICA EN PARTICULAR EN LOS SISTEMAS EN RED DE TRANSMISION NUMERICA DE DATOS, Y EN PARTICULAR A LOS SISTEMAS INFORMATICOS.
ES91401931T 1990-07-11 1991-07-10 Dispositivo de contraste de datos y sistema de transmision numerica de datos resultante. Expired - Lifetime ES2087979T3 (es)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR9008813A FR2664769A1 (fr) 1990-07-11 1990-07-11 Dispositif d'echantillonnage de donnees et systeme de transmission numerique de donnees en resultant.

Publications (1)

Publication Number Publication Date
ES2087979T3 true ES2087979T3 (es) 1996-08-01

Family

ID=9398590

Family Applications (1)

Application Number Title Priority Date Filing Date
ES91401931T Expired - Lifetime ES2087979T3 (es) 1990-07-11 1991-07-10 Dispositivo de contraste de datos y sistema de transmision numerica de datos resultante.

Country Status (7)

Country Link
US (1) US5430773A (es)
EP (1) EP0466593B1 (es)
JP (1) JP2801093B2 (es)
CA (1) CA2046242C (es)
DE (1) DE69118259T2 (es)
ES (1) ES2087979T3 (es)
FR (1) FR2664769A1 (es)

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5619686A (en) * 1993-11-18 1997-04-08 National Semiconductor Corporation Source synchronized data transmission circuit
US5666330A (en) * 1994-07-21 1997-09-09 Telecom Solutions, Inc. Disciplined time scale generator for primary reference clocks
FR2723494B1 (fr) * 1994-08-04 1996-09-06 Bull Sa Procede d'echantillonnage d'un signal numerique en serie
GB9615422D0 (en) * 1996-07-23 1996-09-04 3Com Ireland Digital phase locked loop
US5990813A (en) * 1996-08-27 1999-11-23 Texas Instruments Incorporated Method and apparatus for synchronizing external data to an internal timing signal
JP3338367B2 (ja) * 1998-03-25 2002-10-28 沖電気工業株式会社 位相比較器
US8155236B1 (en) 2002-06-21 2012-04-10 Netlogic Microsystems, Inc. Methods and apparatus for clock and data recovery using transmission lines
US8089887B2 (en) * 2002-11-19 2012-01-03 Massachusetts Institute Of Technology Method for automatic signal routing in ad hoc networks
CN100581095C (zh) * 2003-11-20 2010-01-13 爱德万测试株式会社 时钟恢复电路以及通讯装置
JP4531090B2 (ja) * 2005-03-18 2010-08-25 富士通株式会社 ジッタ抑圧回路
JP5365132B2 (ja) * 2008-10-17 2013-12-11 富士ゼロックス株式会社 直列信号の受信装置、直列伝送システム、直列伝送方法、直列信号の送信装置
US8423814B2 (en) 2010-03-19 2013-04-16 Netlogic Microsystems, Inc. Programmable drive strength in memory signaling

Family Cites Families (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3587043A (en) * 1969-04-29 1971-06-22 Rca Corp Character parity synchronizer
FR2313827A1 (fr) * 1975-06-02 1976-12-31 Materiel Telephonique Systeme de transmission de suites d'elements binaires
US3993957A (en) * 1976-03-08 1976-11-23 International Business Machines Corporation Clock converter circuit
DE2945331C2 (de) * 1979-11-09 1984-05-30 Nixdorf Computer Ag, 4790 Paderborn Vorrichtung in einer Signal-oder Datenverarbeitungsanlage zur Einstellung einer Signalverarbeitungsschaltung
US4449119A (en) * 1981-12-14 1984-05-15 International Business Machines Corporation Self-clocking serial decoder
FR2527029A1 (fr) * 1982-05-14 1983-11-18 Thomson Csf Mat Tel Emetteur et recepteur de donnees en mode paquet
CA1241384A (en) * 1985-10-18 1988-08-30 Stephen C. Carlton Serial-to-parallel converter for high-speed bit streams
JPH0744448B2 (ja) * 1986-03-31 1995-05-15 株式会社東芝 デジタル位相同期ル−プ回路
US4795985A (en) * 1986-04-01 1989-01-03 Hewlett-Packard Company Digital phase lock loop
US4922141A (en) * 1986-10-07 1990-05-01 Western Digital Corporation Phase-locked loop delay line
EP0274606A3 (de) * 1986-11-21 1989-05-03 Siemens Aktiengesellschaft Anordnung zum Bilden einer in integrierter CMOS-Schaltungstechnik realisierten Laufzeitkette und eines Phasenvergleichsgliedes
US4841551A (en) * 1987-01-05 1989-06-20 Grumman Aerospace Corporation High speed data-clock synchronization processor
WO1988005236A1 (en) * 1987-01-05 1988-07-14 Grumman Aerospace Corporation High speed data-clock synchronization processor
JPS63292185A (ja) * 1987-05-25 1988-11-29 日本電気株式会社 デジタル入出力回路
US4873491A (en) * 1987-10-19 1989-10-10 Wilkins Jeffrey K Phase shift circuit utilizing a variable time delay line
US4901076A (en) * 1987-10-29 1990-02-13 International Business Machines Corporation Circuit for converting between serial and parallel data streams by high speed addressing
JP2531742B2 (ja) * 1988-05-17 1996-09-04 株式会社東芝 電圧制御発振回路
ATE101769T1 (de) * 1988-10-13 1994-03-15 Siemens Ag Verfahren und schaltungsanordnung zum empfang eines binaeren digitalsignals.
JPH02260936A (ja) * 1989-03-31 1990-10-23 Toshiba Corp クロック抽出回路
US5018169A (en) * 1989-06-21 1991-05-21 National Semiconductor Corporation High resolution sample clock generator with deglitcher
US4993048A (en) * 1990-04-18 1991-02-12 Unisys Corporation Self-clocking system
US5079519A (en) * 1991-02-14 1992-01-07 Notorola, Inc. Digital phase lock loop for a gate array

Also Published As

Publication number Publication date
JP2801093B2 (ja) 1998-09-21
CA2046242A1 (fr) 1992-01-12
EP0466593A1 (fr) 1992-01-15
EP0466593B1 (fr) 1996-03-27
FR2664769B1 (es) 1994-11-25
CA2046242C (fr) 1995-10-10
DE69118259D1 (de) 1996-05-02
FR2664769A1 (fr) 1992-01-17
JPH07143111A (ja) 1995-06-02
DE69118259T2 (de) 1996-08-22
US5430773A (en) 1995-07-04

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