ES2091606T3 - Sistema de ordenador. - Google Patents

Sistema de ordenador.

Info

Publication number
ES2091606T3
ES2091606T3 ES93909804T ES93909804T ES2091606T3 ES 2091606 T3 ES2091606 T3 ES 2091606T3 ES 93909804 T ES93909804 T ES 93909804T ES 93909804 T ES93909804 T ES 93909804T ES 2091606 T3 ES2091606 T3 ES 2091606T3
Authority
ES
Spain
Prior art keywords
processors
pct
date dec
sec
storage area
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
ES93909804T
Other languages
English (en)
Inventor
Armin Reinmuth
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Siemens AG
Siemens Corp
Original Assignee
Siemens AG
Siemens Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siemens AG, Siemens Corp filed Critical Siemens AG
Application granted granted Critical
Publication of ES2091606T3 publication Critical patent/ES2091606T3/es
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/16—Error detection or correction of the data by redundancy in hardware
    • G06F11/1675—Temporal synchronisation or re-synchronisation of redundant processing components
    • G06F11/1683—Temporal synchronisation or re-synchronisation of redundant processing components at instruction level

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Quality & Reliability (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Multi Processors (AREA)
  • Hardware Redundancy (AREA)
  • Iron Core Of Rotating Electric Machines (AREA)

Abstract

LA INVENCION SE REFIERE A UN SISTEMA DE ORDENADOR QUE DISPONE DE VARIOS PROCESADORES (P1, P2, P3) INTERCONECTADOS, ASOCIADOS CADA UNO DE ELLOS CON UNA MEMORIA (S1, S2, S3). LAS MEMORIAS (S1, S2, S3) DISPONEN TODAS ELLAS DE UNA AREA (SB) DE MEMORIA COMUN A LA QUE TIENEN ACCESO LOS PROCESADORES (P1, P2, P3). PARA SINCRONIZAR LOS CAMBIOS (BZ0, BZ1, BZ2) EN EL ESTADO DE OPERACION DE LOS PROCESADORES (P1, P2, P3) Y/O PARA MANEJAR LOS TRABAJOS DEL PROCESADOR EN UNA MANERA SINCRONA, EL PRIMER PROCESADOR QUE ALCANZA UN PUNTO (MP1, MP2; WP1 ... WP3) DE SINCRONIZACION PREDETERMINADO REGISTRA UN AJUSTE DE DATOS EN EL AREA DE MEMORIA COMUN, ORIGINANDO INTERRUPCION EN LOS CONTROLADORES (IC1, IC2, IC3) ASOCIADOS CON LOS PROCESADORES (P1, P2, P3) PARA GENERAR SEÑALES DE INTERRUPCION Y PARA INICIAR CAMBIOS EN EL ESTADO DE OPERACION DEL PROCESADO DEL TRABAJO DE FORMA SINCRONA. LA INVENCION TIENE APLICACIONES EN MULTIPLES SISTEMAS DE PROCESADORES, SISTEMAS DE ORDENADOR REDUNDANTES Y SISTEMAS DE CONTROL DE PROGRAMA ALMACENADOS.
ES93909804T 1992-06-10 1993-06-01 Sistema de ordenador. Expired - Lifetime ES2091606T3 (es)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
DE4219005A DE4219005A1 (de) 1992-06-10 1992-06-10 Rechnersystem

Publications (1)

Publication Number Publication Date
ES2091606T3 true ES2091606T3 (es) 1996-11-01

Family

ID=6460730

Family Applications (1)

Application Number Title Priority Date Filing Date
ES93909804T Expired - Lifetime ES2091606T3 (es) 1992-06-10 1993-06-01 Sistema de ordenador.

Country Status (7)

Country Link
US (1) US6032173A (es)
EP (1) EP0645034B1 (es)
JP (1) JPH07503565A (es)
AT (1) ATE143154T1 (es)
DE (2) DE4219005A1 (es)
ES (1) ES2091606T3 (es)
WO (1) WO1993025966A1 (es)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE59305660D1 (de) * 1992-11-04 1997-04-10 Siemens Ag Anordnung mit mehreren aktiven und passiven busteilnehmern
DE19809089A1 (de) * 1998-02-25 1999-08-26 Siemens Ag Synchronisations- und/oder Datenaustauschverfahren für sichere, hochverfügbare Rechner und hierzu geeignete Einrichtung
DE10251912A1 (de) * 2002-11-07 2004-05-19 Siemens Ag Synchronisation der Datenverarbeitung in redundanten Datenverarbeitungseinheiten eines Datenverarbeitungssystems
DE102004037017B4 (de) * 2004-07-30 2006-05-18 Siemens Ag Schaltungsanordnung und Verfahren eines Multiprozessorsystems
US20090049323A1 (en) * 2007-08-14 2009-02-19 Imark Robert R Synchronization of processors in a multiprocessor system
EP2615511A1 (de) * 2012-01-12 2013-07-17 Siemens Aktiengesellschaft Verfahren zur synchronen Ausführung von Programmen in einem redundanten Automatisierungssystem

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2253423A5 (es) * 1973-11-30 1975-06-27 Honeywell Bull Soc Ind
US4589066A (en) * 1984-05-31 1986-05-13 General Electric Company Fault tolerant, frame synchronization for multiple processor systems
AU616213B2 (en) * 1987-11-09 1991-10-24 Tandem Computers Incorporated Method and apparatus for synchronizing a plurality of processors
CA2003338A1 (en) * 1987-11-09 1990-06-09 Richard W. Cutts, Jr. Synchronization of fault-tolerant computer system having multiple processors
US4937741A (en) * 1988-04-28 1990-06-26 The Charles Stark Draper Laboratory, Inc. Synchronization of fault-tolerant parallel processing systems
US4985831A (en) * 1988-10-31 1991-01-15 Evans & Sutherland Computer Corp. Multiprocessor task scheduling system
US4965717A (en) * 1988-12-09 1990-10-23 Tandem Computers Incorporated Multiple processor system having shared memory with private-write capability
US5276828A (en) * 1989-03-01 1994-01-04 Digital Equipment Corporation Methods of maintaining cache coherence and processor synchronization in a multiprocessor system using send and receive instructions
DE3911407A1 (de) * 1989-04-07 1990-10-11 Siemens Ag Redundantes rechnersystem
US5212777A (en) * 1989-11-17 1993-05-18 Texas Instruments Incorporated Multi-processor reconfigurable in single instruction multiple data (SIMD) and multiple instruction multiple data (MIMD) modes and method of operation
DE69130630T2 (de) * 1990-09-14 1999-09-09 Hitachi Synchrones Verfahren und Gerät für Prozessoren
US5430850A (en) * 1991-07-22 1995-07-04 Massachusetts Institute Of Technology Data processing system with synchronization coprocessor for multiple threads

Also Published As

Publication number Publication date
WO1993025966A1 (de) 1993-12-23
EP0645034A1 (de) 1995-03-29
EP0645034B1 (de) 1996-09-18
DE4219005A1 (de) 1993-12-16
DE59303892D1 (de) 1996-10-24
US6032173A (en) 2000-02-29
JPH07503565A (ja) 1995-04-13
ATE143154T1 (de) 1996-10-15

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