ES2100207T3 - Prevencion de la determinacion del tiempo para la ejecucion de una predeterminada rutina de proceso de datos en relacion con la realizacion de un suceso externo, observable con anterioridad. - Google Patents

Prevencion de la determinacion del tiempo para la ejecucion de una predeterminada rutina de proceso de datos en relacion con la realizacion de un suceso externo, observable con anterioridad.

Info

Publication number
ES2100207T3
ES2100207T3 ES91301984T ES91301984T ES2100207T3 ES 2100207 T3 ES2100207 T3 ES 2100207T3 ES 91301984 T ES91301984 T ES 91301984T ES 91301984 T ES91301984 T ES 91301984T ES 2100207 T3 ES2100207 T3 ES 2100207T3
Authority
ES
Spain
Prior art keywords
execution
routines
steps
routine
data processing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
ES91301984T
Other languages
English (en)
Inventor
Roy Allen Griffin Iii
Steven Raney Hart
James Neil Esserman
Ron D Katznelson
Steven Edward Anderson
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Arris Technology Inc
Original Assignee
Arris Technology Inc
General Instrument Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Arris Technology Inc, General Instrument Corp filed Critical Arris Technology Inc
Application granted granted Critical
Publication of ES2100207T3 publication Critical patent/ES2100207T3/es
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/04—Digital computers in general; Data processing equipment in general programmed simultaneously with the introduction of data to be processed, e.g. on the same record carrier
    • G—PHYSICS
    • G07—CHECKING-DEVICES
    • G07F—COIN-FREED OR LIKE APPARATUS
    • G07F7/00—Mechanisms actuated by objects other than coins to free or to actuate vending, hiring, coin or paper currency dispensing or refunding apparatus
    • G07F7/08—Mechanisms actuated by objects other than coins to free or to actuate vending, hiring, coin or paper currency dispensing or refunding apparatus by coded identity card or credit card or other personal identification means
    • G07F7/10—Mechanisms actuated by objects other than coins to free or to actuate vending, hiring, coin or paper currency dispensing or refunding apparatus by coded identity card or credit card or other personal identification means together with a coded signal, e.g. in the form of personal identification information, like personal identification number [PIN] or biometric data
    • G07F7/1008—Active credit-cards provided with means to personalise their use, e.g. with PIN-introduction/comparison system
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
    • G06F21/70—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer
    • G06F21/71—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information
    • G06F21/75—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information by inhibiting the analysis of circuitry or operation
    • G06F21/755—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information by inhibiting the analysis of circuitry or operation with measures against power attack
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06Q—INFORMATION AND COMMUNICATION TECHNOLOGY [ICT] SPECIALLY ADAPTED FOR ADMINISTRATIVE, COMMERCIAL, FINANCIAL, MANAGERIAL OR SUPERVISORY PURPOSES; SYSTEMS OR METHODS SPECIALLY ADAPTED FOR ADMINISTRATIVE, COMMERCIAL, FINANCIAL, MANAGERIAL OR SUPERVISORY PURPOSES, NOT OTHERWISE PROVIDED FOR
    • G06Q20/00—Payment architectures, schemes or protocols
    • G06Q20/30—Payment architectures, schemes or protocols characterised by the use of specific devices or networks
    • G06Q20/34—Payment architectures, schemes or protocols characterised by the use of specific devices or networks using cards, e.g. integrated circuit [IC] cards or magnetic cards
    • G06Q20/341—Active cards, i.e. cards including their own processing means, e.g. including an IC or chip
    • G—PHYSICS
    • G07—CHECKING-DEVICES
    • G07F—COIN-FREED OR LIKE APPARATUS
    • G07F7/00—Mechanisms actuated by objects other than coins to free or to actuate vending, hiring, coin or paper currency dispensing or refunding apparatus
    • G07F7/08—Mechanisms actuated by objects other than coins to free or to actuate vending, hiring, coin or paper currency dispensing or refunding apparatus by coded identity card or credit card or other personal identification means
    • G07F7/0806—Details of the card
    • G07F7/0813—Specific details related to card security
    • G07F7/082—Features insuring the integrity of the data on or in the card
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2221/00—Indexing scheme relating to security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
    • G06F2221/21—Indexing scheme relating to G06F21/00 and subgroups addressing additional information or applications relating to security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
    • G06F2221/2123—Dummy operation

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Computer Security & Cryptography (AREA)
  • Business, Economics & Management (AREA)
  • General Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Software Systems (AREA)
  • Mathematical Physics (AREA)
  • Accounting & Taxation (AREA)
  • Strategic Management (AREA)
  • General Business, Economics & Management (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Storage Device Security (AREA)
  • Debugging And Monitoring (AREA)
  • Selective Calling Equipment (AREA)
  • Branch Pipes, Bends, And The Like (AREA)
  • Fire Alarms (AREA)
  • Burglar Alarm Systems (AREA)
  • Retry When Errors Occur (AREA)

Abstract

LA ACTUACION DE UN PROCEDIMIENTO CONOCIDO COMO UN "ATAQUE DE RELOJ" SOBRE UNA RUTINA DE PROCESAMIENTO DE DATOS DE SEGURIDAD (14, 49), SE PREVIENE MEDIANTE UN METODO QUE INHIBE LA SINCRONIZACION CON INSTRUCCIONES GENERADAS EXTERNAMENTE, PREVINIENDO LA DETERMINACION DEL TIEMPO DE EJECUCION DE LA RUTINA DE PROCESAMIENTO DE DATOS PREDETERMINADA EN RELACION CON LA OCURRENCIA DE UN EVENTO EXTERNO OBSERVABLE, QUE PRECEDE A LA EJECUCION DE LA RUTINA PREDETERMINADA. EL METODO INCLUYE LOS PASOS DE (A) VARIACION ALEATORIA DEL TIEMPO ENTRE LA OCURRENCIA DEL EVENTO EXTERNO OBSERVABLE Y LA EJECUCION DE LA RUTINA PREDETERMINADA. EL PASO (A) INCLUYE LOS PASOS (B) EJECUCION DE UNA O MAS RUTINAS DE PROCESAMIENTO DE DATOS INTERMEDIAS (20, 21, 22, 52) ENTRE LA OCURRENCIA DEL EVENTO EXTERNO OBSERVABLE Y LA EJECUCION DE LA RUTINA PREDETERMINADA; Y (C) VARIACION ALEATORIA DE LA DURACION DE LAS MENCIONADAS RUTINAS INTERMEDIAS. LOS PASOS (B) Y (C) PUEDEN INCLUIR EL PASO (D) ENSAMBLAJE ALEATORIO DE M DE DICHAS RUTINAS INTERMEDIAS PARA LA EJECUCION YA MENCIONADA DE ENTRE UN GRUPO (52) DE N RUTINAS ALMACENADAS, TENIENDO DISTINTAS DURACIONES, DONDE M Y N SON ENTEROS, SIENDO N MAYOR QUE M. EL PASO (D) PUEDE INCLUIR CUALQUIERA DE LOS PASOS DE (E) ACCESO ALEATORIO DE DICHAS M RUTINAS INTERMEDIAS EN UNA MEMORIA DE SEGURIDAD (51); O LOS PASOS DE (F) ACCESO ALEATORIO DE PUNTEROS (58) PARA LAS MENCIONADAS M RUTINAS INTERMEDIAS EN UNA MEMORIA DE SEGURIDAD (60); Y (G) EL ACCESO A DICHAS M RUTINAS INTERMEDIAS EN UNA MEMORIA (51) COMO RESPUESTA A LOS MENCIONADOS PUNTEROS. EL PASO (C) INCLUYE LOS PASOS DE (H) VARIACION ALEATORIA DE LA DURACION DE LAS RUTINAS INTERMEDIAS EN RESPUESTA A DATOS PROCESADOS DINAMICAMENTE QUE NO SE PRESENTAN REPETIDOS CADA VEZ QUE SE ACCEDE A LAS RUTINAS INTERMEDIAS. EL METODO INCLUYE ADEMAS LOS PASOS DE (I) MONITORIZACION (26) DE LAS RUTINAS INTERMEDIAS PARA DETECTAR SI ESTAS RUTINAS INTERMEDIAS RECIBEN ALGUN TIPO DE INTROMISION; Y (J) PREVENIR (38) LA EJECUCION DE LA RUTINA PREDETERMINADA EN RESPUESTA A LA DETECCION DE QUE LAS RUTINAS INTERMEDIAS ESTAN SIENDO INTERVENIDAS.
ES91301984T 1990-03-20 1991-03-11 Prevencion de la determinacion del tiempo para la ejecucion de una predeterminada rutina de proceso de datos en relacion con la realizacion de un suceso externo, observable con anterioridad. Expired - Lifetime ES2100207T3 (es)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US49701290A 1990-03-20 1990-03-20

Publications (1)

Publication Number Publication Date
ES2100207T3 true ES2100207T3 (es) 1997-06-16

Family

ID=23975105

Family Applications (1)

Application Number Title Priority Date Filing Date
ES91301984T Expired - Lifetime ES2100207T3 (es) 1990-03-20 1991-03-11 Prevencion de la determinacion del tiempo para la ejecucion de una predeterminada rutina de proceso de datos en relacion con la realizacion de un suceso externo, observable con anterioridad.

Country Status (11)

Country Link
EP (1) EP0448262B1 (es)
JP (1) JP3611867B2 (es)
KR (1) KR100216937B1 (es)
AT (1) ATE152530T1 (es)
AU (1) AU637677B2 (es)
CA (1) CA2037857C (es)
DE (1) DE69125881T2 (es)
DK (1) DK0448262T3 (es)
ES (1) ES2100207T3 (es)
GR (1) GR3023851T3 (es)
IE (1) IE74155B1 (es)

Families Citing this family (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2745924B1 (fr) * 1996-03-07 1998-12-11 Bull Cp8 Circuit integre perfectionne et procede d'utilisation d'un tel circuit integre
FR2765361B1 (fr) * 1997-06-26 2001-09-21 Bull Cp8 Microprocesseur ou microcalculateur imprevisible
ES2660057T3 (es) * 1998-05-18 2018-03-20 Giesecke + Devrient Mobile Security Gmbh Soporte de almacenamiento de datos de acceso protegido
RU2263967C2 (ru) * 1998-05-18 2005-11-10 Гизеке Унд Девриент Гмбх Защищенный от несанкционированного доступа носитель данных, способ выполнения в нем операций, в том числе относящихся к защите данных, и способ защиты конфиденциальных данных
ATE474278T1 (de) 1998-07-31 2010-07-15 Nxp Bv Datenverarbeitungsgerät mit mitteln zum entgegenwirken von analyseverfahren zur entdeckung eines geheimen charakteristischen wertes
DE19837808A1 (de) * 1998-08-20 2000-02-24 Orga Kartensysteme Gmbh Verfahren zur Ausführung eines Verschlüsselungsprogramms zur Verschlüsselung von Daten in einem mikroprozessorgestützten, tragbaren Datenträger
FR2784763B1 (fr) * 1998-10-16 2001-10-19 Gemplus Card Int Composant electronique et procede pour masquer l'execution d'instructions ou la manipulation de donnees
US6408075B1 (en) 1998-11-30 2002-06-18 Hitachi, Ltd. Information processing equipment and IC card
JP2000165375A (ja) 1998-11-30 2000-06-16 Hitachi Ltd 情報処理装置、ｉｃカード
JP4317607B2 (ja) 1998-12-14 2009-08-19 株式会社日立製作所 情報処理装置、耐タンパ処理装置
FR2787900B1 (fr) * 1998-12-28 2001-02-09 Bull Cp8 Circuit integre intelligent
FR2790347B1 (fr) * 1999-02-25 2001-10-05 St Microelectronics Sa Procede de securisation d'un enchainement d'operations realisees par un circuit electronique dans le cadre de l'execution d'un algorithme
JP2001118042A (ja) * 1999-10-19 2001-04-27 Hitachi Ltd カード監視方法
FR2849232B1 (fr) * 2002-12-24 2005-02-25 Trusted Logic Procede pour la securisation des systemes informatiques incorporant un module d'interpretation de code
US20040162993A1 (en) * 2003-02-13 2004-08-19 Yannick Teglia Antifraud method of an algorithm executed by an integrated circuit
DE10307797B4 (de) * 2003-02-24 2010-11-11 Infineon Technologies Ag Vorrichtung und Verfahren zum Ermitteln einer Unregelmäßigkeit in einem Ablauf eines Nutzprogramms
IL171963A0 (en) 2005-11-14 2006-04-10 Nds Ltd Secure read-write storage device
US10785259B2 (en) 2016-04-19 2020-09-22 Mitsubishi Electric Corporation Relay device
FR3075430B1 (fr) * 2017-12-20 2020-08-07 Oberthur Technologies Procede de traitement de donnees et dispositif electronique associe

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4494114B1 (en) * 1983-12-05 1996-10-15 Int Electronic Tech Security arrangement for and method of rendering microprocessor-controlled electronic equipment inoperative after occurrence of disabling event
JPS60207957A (ja) * 1984-03-31 1985-10-19 Toshiba Corp デ−タ保護方式

Also Published As

Publication number Publication date
EP0448262A2 (en) 1991-09-25
JP3611867B2 (ja) 2005-01-19
JPH04223530A (ja) 1992-08-13
KR910017304A (ko) 1991-11-05
EP0448262A3 (en) 1992-09-30
DE69125881D1 (de) 1997-06-05
AU637677B2 (en) 1993-06-03
CA2037857A1 (en) 1991-09-21
DE69125881T2 (de) 1997-08-14
IE910851A1 (en) 1991-09-25
ATE152530T1 (de) 1997-05-15
CA2037857C (en) 2001-01-16
AU7291591A (en) 1991-09-26
EP0448262B1 (en) 1997-05-02
GR3023851T3 (en) 1997-09-30
KR100216937B1 (ko) 1999-09-01
IE74155B1 (en) 1997-07-02
DK0448262T3 (da) 1997-10-27

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