ES2100974T3 - Disposicion integrada de memoria de semiconductores. - Google Patents

Disposicion integrada de memoria de semiconductores.

Info

Publication number
ES2100974T3
ES2100974T3 ES92109689T ES92109689T ES2100974T3 ES 2100974 T3 ES2100974 T3 ES 2100974T3 ES 92109689 T ES92109689 T ES 92109689T ES 92109689 T ES92109689 T ES 92109689T ES 2100974 T3 ES2100974 T3 ES 2100974T3
Authority
ES
Spain
Prior art keywords
data
delivery
provision
main memory
sections
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
ES92109689T
Other languages
English (en)
Inventor
Rainer Dr Dr-Ing Luder
Willibald Dipl-Ing Meyer
Bodo Dr Dr-Ing Braun
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Siemens AG
Siemens Corp
Original Assignee
Siemens AG
Siemens Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siemens AG, Siemens Corp filed Critical Siemens AG
Application granted granted Critical
Publication of ES2100974T3 publication Critical patent/ES2100974T3/es
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N5/00—Details of television systems
    • H04N5/76—Television signal recording
    • H04N5/907—Television signal recording using static stores, e.g. storage tubes or semiconductor memories
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/36—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of a graphic pattern, e.g. using an all-points-addressable [APA] memory
    • G09G5/39—Control of the bit-mapped memory
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1075—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers for multiport memories each having random access ports and serial ports, e.g. video RAM
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2360/00—Aspects of the architecture of display systems
    • G09G2360/12—Frame memory handling
    • G09G2360/126—The frame memory having additional data ports, not inclusive of standard details of the output serial port of a VRAM

Landscapes

  • Engineering & Computer Science (AREA)
  • Multimedia (AREA)
  • Signal Processing (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Dram (AREA)

Abstract

DISPOSICION DE MEMORIA, EN PARTICULAR PARA EL ALMACENAMIENTO DE DATOS DE PUNTO DE IMAGEN DE UNA IMAGEN DE TELEVISION -CON UNA MEMORIA (50) PRINCIPAL -CON AL MENOS UNA DISPOSICION (100) DE SOLICITUD, QUE ES CONMUTABLE DE FORMA CONJUNTA CON UN REGISTRO (101) DE DESPLAZAMIENTO COMPUESTO AL MENOS DE DOS TRAMOS PARA LA INTRODUCCION EN SERIE DE DATOS DE PUNTO DE IMAGEN, CON UN REGISTRO (102) DE ESCRITURA COMPUESTO AL MENOS DE DOS TRAMOS PARA LA ENTREGA DE DATOS DE FORMA DE BIT PARALELOS EN LA MEMORIA (50) PRINCIPAL A TRAVES DE UN BUS (10) DE DATOS, CON UN DISPOSITIVO (103) DE CONMUTACION PARA EL CONTROL DE ESTA ENTREGA DE DATOS A LA MEMORIA (50) PRINCIPAL Y CONFORMADO CON UN INTERRUPTOR (104), Y QUE ES CONMUTABLE DE FORMA CONJUNTA AL MENOS CON UNA OTRA DISPOSICION (200) DE SOLICITUD, -CON AL MENOS UNA DISPOSICION (300) DE ENTREGA, QUE ESTA CONFIGURADA CON UN REGISTRO (301) DE DESPLAZAMIENTO COMPUESTO AL MENOS DE DOS TRAMOS PARA LA SELECCION EN SERIE DE DATOS DE PUNTO DE IMAGEN, CON UNA MEMORIA (302) DE LECTURA COMPUESTA AL MENOS DE DOS TRAMOS PARA LA RECEPCION PARALELA DE BITS DE DATOS A PARTIR DE LA MEMORIA (50) PRINCIPAL POR MEDIO DEL BUS (10) DE DATOS CON UN DISPOSITIVO (303) DE CONMUTACION PARA EL CONTROL DE ESTA RECEPCION DE DATOS DE LA MEMORIA (50) PRINCIPAL Y CON UN INTERRUPTOR (304), Y QUE ES CONMUTABLE DE FORMA CONJUNTA CON AL MENOS UNA OTRA DISPOSICION (400) DE ENTREGA, -Y CON UN CIRCUITO (20) DE CONTROL, QUE CONTROLA EL FLUJO DE DATOS ENTRE LA DISPOSICION (100) DE SOLICITUD Y LA SOLICITUD (300) DE ENTREGA Y LA MEMORIA (50) PRINCIPAL, Y QUE CONTROLA TAMBIEN LA RESPECTIVA INTERCONEXION DE LAS DISPOSICIONES (100,200) DE SOLICITUD Y/O LAS DISPOSICIONES (300,400) DE ENTREGA, EN DONDE SON CONTROLABLES AL MENOS A TRAVES DE UNA PRIMERA CONEXION (1,2,3) EXTERNA.
ES92109689T 1992-06-09 1992-06-09 Disposicion integrada de memoria de semiconductores. Expired - Lifetime ES2100974T3 (es)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
EP19920109689 EP0573685B1 (de) 1992-06-09 1992-06-09 Integrierte Halbleiterspeicheranordnung

Publications (1)

Publication Number Publication Date
ES2100974T3 true ES2100974T3 (es) 1997-07-01

Family

ID=8209693

Family Applications (1)

Application Number Title Priority Date Filing Date
ES92109689T Expired - Lifetime ES2100974T3 (es) 1992-06-09 1992-06-09 Disposicion integrada de memoria de semiconductores.

Country Status (3)

Country Link
EP (1) EP0573685B1 (es)
DE (1) DE59208431D1 (es)
ES (1) ES2100974T3 (es)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH09507310A (ja) * 1994-01-04 1997-07-22 ハネウエル・インコーポレーテッド ラスタ・エンハンスメント機構を備えた再構成可能なビデオ出力アーキテクチャ
US6349058B1 (en) * 2001-02-16 2002-02-19 Microchip Technology Incorporated Electronic circuit and method for storing configuration and calibration information in a non-volatile memory array

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CA1293565C (en) * 1986-04-28 1991-12-24 Norio Ebihara Semiconductor memory
FR2630876A1 (fr) * 1988-04-29 1989-11-03 Trt Telecom Radio Electr Element de circuit ´ point de croisement entre deux lignes omnibus
DE3907722A1 (de) * 1989-03-10 1990-09-13 Philips Patentverwaltung Speicheranordnung

Also Published As

Publication number Publication date
EP0573685A1 (de) 1993-12-15
EP0573685B1 (de) 1997-05-02
DE59208431D1 (de) 1997-06-05

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