ES2104681T3 - Procedimiento y dispositivo de interconexion de circuitos integrados en tres dimensiones. - Google Patents
Procedimiento y dispositivo de interconexion de circuitos integrados en tres dimensiones.Info
- Publication number
- ES2104681T3 ES2104681T3 ES91403307T ES91403307T ES2104681T3 ES 2104681 T3 ES2104681 T3 ES 2104681T3 ES 91403307 T ES91403307 T ES 91403307T ES 91403307 T ES91403307 T ES 91403307T ES 2104681 T3 ES2104681 T3 ES 2104681T3
- Authority
- ES
- Spain
- Prior art keywords
- interconnection
- plates
- dimensions
- procedure
- integrated circuits
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W99/00—Subject matter not provided for in other groups of this subclass
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/071—Connecting or disconnecting
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/834—Interconnections on sidewalls of chips
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/20—Configurations of stacked chips
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/20—Configurations of stacked chips
- H10W90/22—Configurations of stacked chips the stacked chips being on both top and bottom sides of a package substrate, interposer or RDL
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Turning (AREA)
- Numerical Control (AREA)
- Automatic Control Of Machine Tools (AREA)
- Auxiliary Devices For Machine Tools (AREA)
- Wire Bonding (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
Abstract
LA PRESENTE INVENCION SE REFIERE A UN PROCESO Y UN DISPOSITIVO PARA LA INTERCONEXION DE PLACAS SEMICONDUCTORAS APILADAS, CONTENIENDO CADA UNA DE LAS PLACAS UN CIRCUITO INTEGRADO. POR ESTE PROPOSITO, LAS PLACAS SEMICONDUCTORAS (P) ESTAN APILADAS Y HECHAS SOLIDARIAS UNAS DE OTRAS. EN UN MODO DE REALIZACION, SUS BORNES DE CONEXION ESTAN CADA UNO CONECTADOS MEDIANTE UN HILO (F) A UNA CARA CUALQUIERA DEL APILAMIENTO SALVO UNA (B), DESTINADA A ESTAR EN CONTACTO CON UN CIRCUITO IMPRESO. LA CONEXION DE LAS PLACAS ENTRE SI Y DE ESTAS ULTIMAS CON EL CIRCUITO IMPRESO, SE REALIZA SOBRE LAS CARAS (F SUB V, F SUB S, F SUB L) DEL APILAMIENTO.
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| FR9015473A FR2670323B1 (fr) | 1990-12-11 | 1990-12-11 | Procede et dispositif d'interconnexion de circuits integres en trois dimensions. |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| ES2104681T3 true ES2104681T3 (es) | 1997-10-16 |
Family
ID=9403101
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| ES91403307T Expired - Lifetime ES2104681T3 (es) | 1990-12-11 | 1991-12-06 | Procedimiento y dispositivo de interconexion de circuitos integrados en tres dimensiones. |
Country Status (7)
| Country | Link |
|---|---|
| EP (1) | EP0490739B1 (es) |
| JP (1) | JP3415621B2 (es) |
| KR (1) | KR920704344A (es) |
| DE (1) | DE69126599T2 (es) |
| ES (1) | ES2104681T3 (es) |
| FR (1) | FR2670323B1 (es) |
| WO (1) | WO1992010853A1 (es) |
Families Citing this family (28)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5847448A (en) * | 1990-12-11 | 1998-12-08 | Thomson-Csf | Method and device for interconnecting integrated circuits in three dimensions |
| FR2688629A1 (fr) * | 1992-03-10 | 1993-09-17 | Thomson Csf | Procede et dispositif d'encapsulation en trois dimensions de pastilles semi-conductrices. |
| FR2688630B1 (fr) * | 1992-03-13 | 2001-08-10 | Thomson Csf | Procede et dispositif d'interconnexion en trois dimensions de boitiers de composants electroniques. |
| HUT73312A (en) * | 1992-09-14 | 1996-07-29 | Badehi | Method and apparatus for producing integrated circuit devices, and integrated circuit device |
| FR2696871B1 (fr) * | 1992-10-13 | 1994-11-18 | Thomson Csf | Procédé d'interconnexion 3D de boîtiers de composants électroniques, et composants 3D en résultant. |
| IL106892A0 (en) * | 1993-09-02 | 1993-12-28 | Pierre Badehi | Methods and apparatus for producing integrated circuit devices |
| IL108359A (en) * | 1994-01-17 | 2001-04-30 | Shellcase Ltd | Method and apparatus for producing integrated circuit devices |
| US5675180A (en) | 1994-06-23 | 1997-10-07 | Cubic Memory, Inc. | Vertical interconnect process for silicon segments |
| US6255726B1 (en) | 1994-06-23 | 2001-07-03 | Cubic Memory, Inc. | Vertical interconnect process for silicon segments with dielectric isolation |
| US6124633A (en) * | 1994-06-23 | 2000-09-26 | Cubic Memory | Vertical interconnect process for silicon segments with thermally conductive epoxy preform |
| US6080596A (en) * | 1994-06-23 | 2000-06-27 | Cubic Memory Inc. | Method for forming vertical interconnect process for silicon segments with dielectric isolation |
| US5891761A (en) * | 1994-06-23 | 1999-04-06 | Cubic Memory, Inc. | Method for forming vertical interconnect process for silicon segments with thermally conductive epoxy preform |
| US6486528B1 (en) | 1994-06-23 | 2002-11-26 | Vertical Circuits, Inc. | Silicon segment programming apparatus and three terminal fuse configuration |
| US6117707A (en) * | 1994-07-13 | 2000-09-12 | Shellcase Ltd. | Methods of producing integrated circuit devices |
| US6624505B2 (en) | 1998-02-06 | 2003-09-23 | Shellcase, Ltd. | Packaged integrated circuits and methods of producing thereof |
| IL123207A0 (en) | 1998-02-06 | 1998-09-24 | Shellcase Ltd | Integrated circuit device |
| FR2785452B1 (fr) * | 1998-11-03 | 2003-06-13 | Tda Armements Sas | Procede de realisation de recepteurs d'ondes radioelectriques par interconnexion de circuits integres en trois dimensions |
| FR2802706B1 (fr) | 1999-12-15 | 2002-03-01 | 3D Plus Sa | Procede et dispositif d'interconnexion en trois dimensions de composants electroniques |
| AU2002216352A1 (en) | 2000-12-21 | 2002-07-01 | Shellcase Ltd. | Packaged integrated circuits and methods of producing thereof |
| US7033664B2 (en) | 2002-10-22 | 2006-04-25 | Tessera Technologies Hungary Kft | Methods for producing packaged integrated circuit devices and packaged integrated circuit devices produced thereby |
| US7566853B2 (en) | 2005-08-12 | 2009-07-28 | Tessera, Inc. | Image sensor employing a plurality of photodetector arrays and/or rear-illuminated architecture |
| RU2336595C2 (ru) * | 2006-09-01 | 2008-10-20 | Александр Иванович Завадский | Способ изготовления объемных мини-модулей для радиоэлектронной аппаратуры |
| WO2010026527A2 (en) | 2008-09-08 | 2010-03-11 | Koninklijke Philips Electronics N.V. | Radiation detector with a stack of converter plates and interconnect layers |
| FR2940521B1 (fr) | 2008-12-19 | 2011-11-11 | 3D Plus | Procede de fabrication collective de modules electroniques pour montage en surface |
| EP2202789A1 (en) * | 2008-12-24 | 2010-06-30 | Nxp B.V. | Stack of molded integrated circuit dies with side surface contact tracks |
| JP5264640B2 (ja) * | 2009-07-24 | 2013-08-14 | 新光電気工業株式会社 | 積層型半導体装置及びその製造方法 |
| RU2460171C2 (ru) * | 2010-08-23 | 2012-08-27 | Федеральное государственное унитарное предприятие Омский научно-исследовательский институт приборостроения (ФГУП ОНИИП) | Объемный модуль для радиоэлектронной аппаратуры |
| DE102016104626A1 (de) | 2015-03-16 | 2016-09-22 | Jtekt Corporation | Spindelvorrichtung |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3746934A (en) * | 1971-05-06 | 1973-07-17 | Siemens Ag | Stack arrangement of semiconductor chips |
| DE2919998A1 (de) * | 1979-05-17 | 1980-11-27 | Siemens Ag | Befestigen der anschlussdraehte von halbleitersystemen auf den traegerelementen |
| FR2645681B1 (fr) * | 1989-04-07 | 1994-04-08 | Thomson Csf | Dispositif d'interconnexion verticale de pastilles de circuits integres et son procede de fabrication |
-
1990
- 1990-12-11 FR FR9015473A patent/FR2670323B1/fr not_active Expired - Fee Related
-
1991
- 1991-12-06 DE DE69126599T patent/DE69126599T2/de not_active Expired - Lifetime
- 1991-12-06 JP JP50211392A patent/JP3415621B2/ja not_active Expired - Lifetime
- 1991-12-06 EP EP91403307A patent/EP0490739B1/fr not_active Expired - Lifetime
- 1991-12-06 WO PCT/FR1991/000978 patent/WO1992010853A1/fr not_active Ceased
- 1991-12-06 ES ES91403307T patent/ES2104681T3/es not_active Expired - Lifetime
- 1991-12-06 KR KR1019920701892A patent/KR920704344A/ko not_active Abandoned
Also Published As
| Publication number | Publication date |
|---|---|
| FR2670323A1 (fr) | 1992-06-12 |
| DE69126599T2 (de) | 1997-10-02 |
| EP0490739B1 (fr) | 1997-06-18 |
| JPH05505067A (ja) | 1993-07-29 |
| KR920704344A (ko) | 1992-12-19 |
| WO1992010853A1 (fr) | 1992-06-25 |
| DE69126599D1 (de) | 1997-07-24 |
| FR2670323B1 (fr) | 1997-12-12 |
| JP3415621B2 (ja) | 2003-06-09 |
| EP0490739A1 (fr) | 1992-06-17 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| FG2A | Definitive protection |
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