ES2109448T3 - Sistema de soporte logico de objetos replicados que explotan una mensajeria dinamica, particularmente para instalacion de control/mando con arquitectura redundante. - Google Patents

Sistema de soporte logico de objetos replicados que explotan una mensajeria dinamica, particularmente para instalacion de control/mando con arquitectura redundante.

Info

Publication number
ES2109448T3
ES2109448T3 ES93401325T ES93401325T ES2109448T3 ES 2109448 T3 ES2109448 T3 ES 2109448T3 ES 93401325 T ES93401325 T ES 93401325T ES 93401325 T ES93401325 T ES 93401325T ES 2109448 T3 ES2109448 T3 ES 2109448T3
Authority
ES
Spain
Prior art keywords
processor
control
exploit
support system
objects
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
ES93401325T
Other languages
English (en)
Inventor
Christophe Baradel
Yves Eychenne
Bruno Kohen
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Alcatel Lucent SAS
Original Assignee
Alcatel Alsthom Compagnie Generale dElectricite
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Alcatel Alsthom Compagnie Generale dElectricite filed Critical Alcatel Alsthom Compagnie Generale dElectricite
Application granted granted Critical
Publication of ES2109448T3 publication Critical patent/ES2109448T3/es
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/16—Error detection or correction of the data by redundancy in hardware
    • G06F11/20—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements
    • G06F11/2097—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements maintaining the standby controller/processing unit updated
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/16—Error detection or correction of the data by redundancy in hardware
    • G06F11/20—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements
    • G06F11/202—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements where processing functionality is redundant
    • G06F11/2038—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements where processing functionality is redundant with a single idle spare processing component
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/16—Error detection or correction of the data by redundancy in hardware
    • G06F11/20—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements
    • G06F11/202—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements where processing functionality is redundant
    • G06F11/2041—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements where processing functionality is redundant with more than one idle spare processing component

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Quality & Reliability (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Hardware Redundancy (AREA)
  • Multi Processors (AREA)
  • Computer And Data Communications (AREA)
  • Stored Programmes (AREA)

Abstract

LA INVENCION TRATA SOBRE UN SISTEMA LOGICO DE OBJETOS REPLICADOS QUE PERMITE DIRIGIR UNA INSTALACION DE CONTROL/MANDO DE ARQUITECTURA REDUNDANTE QUE COMPRENDE AL MENOS UN PRIMER PROCESADOR (1) Y UN SEGUNDO PROCESADOR (1''). EL SISTEMA LOGICO (2) COMPRENDE UNOS OBJETOS LOGICALES (3) QUE COMUNICAN ENTRE ELLOS POR MENSAJES A TRAVES DE UN MECANISMO DE MENSAJERIA DE OBJETO DINAMICO. UNA REPLICA (2'') DEL SISTEMA LOGICO (2) RESIDE EN EL SEGUNDO PROCESADOR (1''). CIERTOS OBJETOS (3) DEL SISTEMA LOGICO (2) SON MARCADOS Y LA MENSAJERIA DE OBJETOS DINAMICO (5) INCLUYE ADEMAS UN MEDIO DE CONTROL (51) PARA IDENTIFICAR UN MENSAJE DE OBJETO DESTINADO A UN OBJETO MARCADO Y UN MEDIO (52) PARA PASAR EL CONTENIDO DEL MENSAJE DE OBJETO, BAJO FORMA DE UN MENSAJE RED, AL SEGUNDO PROCESADOR (1''). EN RESPUESTA AL MENSAJE RED, LA MENSAJERIA DE OBJETO DINAMICO (5'') EN EL SEGUNDO PROCESADOR (1'') ACTIVA EL REPLICADO (3'') DEL OBJETO MARCADO (3). LA INVENCION PERMITE PONER EN MARCHA UNA TECNICA DE REDUNDANCIA SEMIACTIVA.
ES93401325T 1992-05-25 1993-05-24 Sistema de soporte logico de objetos replicados que explotan una mensajeria dinamica, particularmente para instalacion de control/mando con arquitectura redundante. Expired - Lifetime ES2109448T3 (es)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR9206372A FR2691559B1 (fr) 1992-05-25 1992-05-25 Systeme logiciel a objets repliques exploitant une messagerie dynamique, notamment pour installation de controle/commande a architecture redondante.

Publications (1)

Publication Number Publication Date
ES2109448T3 true ES2109448T3 (es) 1998-01-16

Family

ID=9430141

Family Applications (1)

Application Number Title Priority Date Filing Date
ES93401325T Expired - Lifetime ES2109448T3 (es) 1992-05-25 1993-05-24 Sistema de soporte logico de objetos replicados que explotan una mensajeria dinamica, particularmente para instalacion de control/mando con arquitectura redundante.

Country Status (7)

Country Link
US (1) US5488723A (es)
EP (1) EP0572307B1 (es)
JP (1) JPH06509674A (es)
DE (1) DE69315378T2 (es)
ES (1) ES2109448T3 (es)
FR (1) FR2691559B1 (es)
WO (1) WO1993024884A1 (es)

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US7844665B2 (en) * 2004-04-23 2010-11-30 Waratek Pty Ltd. Modified computer architecture having coordinated deletion of corresponding replicated memory locations among plural computers
US20060095483A1 (en) * 2004-04-23 2006-05-04 Waratek Pty Limited Modified computer architecture with finalization of objects
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US7581069B2 (en) * 2005-10-25 2009-08-25 Waratek Pty Ltd. Multiple computer system with enhanced memory clean up
US8015236B2 (en) * 2005-10-25 2011-09-06 Waratek Pty. Ltd. Replication of objects having non-primitive fields, especially addresses
US20070100828A1 (en) * 2005-10-25 2007-05-03 Holt John M Modified machine architecture with machine redundancy
US7761670B2 (en) * 2005-10-25 2010-07-20 Waratek Pty Limited Modified machine architecture with advanced synchronization
US7958322B2 (en) * 2005-10-25 2011-06-07 Waratek Pty Ltd Multiple machine architecture with overhead reduction
US7849369B2 (en) * 2005-10-25 2010-12-07 Waratek Pty Ltd. Failure resistant multiple computer system and method
US7660960B2 (en) * 2005-10-25 2010-02-09 Waratek Pty, Ltd. Modified machine architecture with partial memory updating
RU2419845C2 (ru) * 2006-03-28 2011-05-27 Панасоник Электрик Воркс Ко., Лтд. Сетевая система
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US20080130652A1 (en) * 2006-10-05 2008-06-05 Holt John M Multiple communication networks for multiple computers
US20080133691A1 (en) * 2006-10-05 2008-06-05 Holt John M Contention resolution with echo cancellation
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Also Published As

Publication number Publication date
FR2691559B1 (fr) 1997-01-03
WO1993024884A1 (fr) 1993-12-09
DE69315378T2 (de) 1998-03-19
US5488723A (en) 1996-01-30
JPH06509674A (ja) 1994-10-27
DE69315378D1 (de) 1998-01-08
EP0572307A1 (fr) 1993-12-01
FR2691559A1 (fr) 1993-11-26
EP0572307B1 (fr) 1997-11-26

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