ES2142373T3 - Metodo de encaminamiento para diagrama de red. - Google Patents

Metodo de encaminamiento para diagrama de red.

Info

Publication number
ES2142373T3
ES2142373T3 ES94201516T ES94201516T ES2142373T3 ES 2142373 T3 ES2142373 T3 ES 2142373T3 ES 94201516 T ES94201516 T ES 94201516T ES 94201516 T ES94201516 T ES 94201516T ES 2142373 T3 ES2142373 T3 ES 2142373T3
Authority
ES
Spain
Prior art keywords
level
elements
coordinates
virtual
network diagram
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
ES94201516T
Other languages
English (en)
Inventor
Tamotsu Nishiyama
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Application granted granted Critical
Publication of ES2142373T3 publication Critical patent/ES2142373T3/es
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/10—Geometric CAD
    • G06F30/18—Network design, e.g. design based on topological or interconnect aspects of utility systems, piping, heating ventilation air conditioning [HVAC] or cabling
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2111/00—Details relating to CAD techniques
    • G06F2111/12—Symbolic schematics

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Geometry (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Analysis (AREA)
  • Mathematical Optimization (AREA)
  • Pure & Applied Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Evolutionary Computation (AREA)
  • Computational Mathematics (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Software Systems (AREA)
  • Mathematical Physics (AREA)
  • Data Mining & Analysis (AREA)
  • Databases & Information Systems (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Image Analysis (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)
  • Position Fixing By Use Of Radio Waves (AREA)
  • Mobile Radio Communication Systems (AREA)
  • Communication Control (AREA)
  • Circuits Of Receivers In General (AREA)
  • Small-Scale Networks (AREA)
  • Image Processing (AREA)
  • Devices Affording Protection Of Roads Or Walls For Sound Insulation (AREA)
  • Information Retrieval, Db Structures And Fs Structures Therefor (AREA)
  • Financial Or Insurance-Related Operations Such As Payment And Settlement (AREA)
  • Medicines Containing Material From Animals Or Micro-Organisms (AREA)
  • General Factory Administration (AREA)
  • Exchange Systems With Centralized Control (AREA)
  • Structure Of Telephone Exchanges (AREA)

Abstract

SE PRESENTAN UNIDADES (1-5) O PASOS DE PROCESAMIENTO (11-16) RESPECTIVAMENTE PARA DETECTAR LOS BUCLES DE UN CIRCUITO LOGICO Y DETERMINAR ASI LOS NIVELES LOGICOS (COMPUERTAS) ASOCIADOS A UNAS PRIMERAS COORDENADAS DE ELEMENTOS RESPECTIVOS DE TAL MODO QUE EL LUGAR DONDE SE PRODUCE EL NIVEL MAXIMO DE SUPERPOSICION DE LOS BUCLES PUEDA SER ASIGNADO A MODO DE DIRECCIONAMIENTO DE REALIMENTACION, PARA DETERMINAR LAS RELACIONES DE POSICION ENTRE LOS ELEMENTOS EN EL NIVEL DE REFERENCIA PARA DESCONGESTIONAR LOS DIRECCIONAMIENTOS CERCA DEL NIVEL DE REFERENCIA Y ASI OBTENER SECUENCIALMENTE UNA CORRESPONDENCIA MAXIMA EN UN GRAFICO BIPARTITO CONSTITUIDO POR RELACIONES CONECTIVAS DE LOS ELEMENTOS DE CADA NIVEL EMPEZANDO POR EL NIVEL DE REFERENCIA PARA DETERMINAR LAS RELACIONES DE POSICION RELACIONADAS A UNAS SEGUNDAS COORDINADAS PARA ASI ASIGNAR LA MISMA POSICION A LOS ELEMENTOS ASOCIADOS ENTRE SI Y PARA DEFINIR UN TRAMO DE DIRECCIONAMIENTO VIRTUAL PARA ASI CONSEGUIR UN DIRECCIONAMIENTO QUE SE CORRESPONDA CON UN RESULTADO DE CLASIFICACION MEDIANTE EL USO DE TRAMOS DE DIRECCIONAMIENTO VIRTUALES.
ES94201516T 1988-09-09 1989-09-07 Metodo de encaminamiento para diagrama de red. Expired - Lifetime ES2142373T3 (es)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP63227030A JPH0786883B2 (ja) 1988-09-09 1988-09-09 網図または諭理回路図自動生成方法およびそのシステム

Publications (1)

Publication Number Publication Date
ES2142373T3 true ES2142373T3 (es) 2000-04-16

Family

ID=16854419

Family Applications (3)

Application Number Title Priority Date Filing Date
ES94201516T Expired - Lifetime ES2142373T3 (es) 1988-09-09 1989-09-07 Metodo de encaminamiento para diagrama de red.
ES94201515T Expired - Lifetime ES2134895T3 (es) 1988-09-09 1989-09-07 Metodo para la colocacion de nudos en un diagrama de base grafica.
ES99202311T Expired - Lifetime ES2285815T3 (es) 1988-09-09 1989-09-07 Metodo de encaminamiento automatico para un circuito logico.

Family Applications After (2)

Application Number Title Priority Date Filing Date
ES94201515T Expired - Lifetime ES2134895T3 (es) 1988-09-09 1989-09-07 Metodo para la colocacion de nudos en un diagrama de base grafica.
ES99202311T Expired - Lifetime ES2285815T3 (es) 1988-09-09 1989-09-07 Metodo de encaminamiento automatico para un circuito logico.

Country Status (7)

Country Link
US (1) US5550714A (es)
EP (6) EP0612021B1 (es)
JP (1) JPH0786883B2 (es)
KR (1) KR930001025B1 (es)
AT (6) ATE363103T1 (es)
DE (6) DE68929052T2 (es)
ES (3) ES2142373T3 (es)

Families Citing this family (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2612967B2 (ja) * 1991-01-18 1997-05-21 松下電器産業株式会社 網図自動生成方法及びそのシステム
JPH04365162A (ja) * 1991-06-13 1992-12-17 Matsushita Electric Ind Co Ltd 資源割当解析方法とスケジューリング方法およびそのシステム
DE4437744A1 (de) * 1994-10-21 1996-04-25 Test Plus Electronic Gmbh Verfahren zum Auffinden und zur Darstellung von Schaltungselementen einer elektronischen Schaltung für die Funktionsprüfung der Schaltung
JP3608832B2 (ja) * 1995-02-28 2005-01-12 富士通株式会社 自動配線方法および自動配線装置
US5731983A (en) * 1995-12-29 1998-03-24 Nec Usa, Inc. Method for synthesizing a sequential circuit
US5808896A (en) * 1996-06-10 1998-09-15 Micron Technology, Inc. Method and system for creating a netlist allowing current measurement through a sub-circuit
US5875115A (en) * 1996-08-06 1999-02-23 Micron Technology, Inc. System and method for scoping global nets in a flat netlist
US5901064A (en) * 1996-08-06 1999-05-04 Micron Technology, Inc. System and method for scoping global nets in a hierarchical netlist
US7076410B1 (en) * 1997-01-27 2006-07-11 Unisys Corporation Method and apparatus for efficiently viewing a number of selected components using a database editor tool
US6009249A (en) 1997-06-13 1999-12-28 Micron Technology, Inc. Automated load determination for partitioned simulation
US7394760B1 (en) * 2003-07-09 2008-07-01 Sprint Communications Company L.P. Method and system for correlating practical constraints in a network
US7146594B1 (en) 2003-12-15 2006-12-05 Ugs Corp. System, method, and computer program product for schematic generation
JP2007087215A (ja) * 2005-09-22 2007-04-05 Hitachi Ltd ハードウェアモデルの変換処理に用いられるデータ構造、コンピュータプログラム、方法、及びシステム
JP2007149061A (ja) * 2005-10-31 2007-06-14 Seiko Epson Corp レイアウトシステムおよびレイアウトプログラム、並びにレイアウト方法
JP2010033493A (ja) * 2008-07-31 2010-02-12 Sony Corp レイアウト配線混雑予測装置およびその方法、並びにプログラム
CN106802970B (zh) * 2015-11-26 2020-05-19 英业达科技有限公司 印刷电路板布局方法及系统
CN112180817B (zh) * 2019-07-02 2021-11-16 北京东土科技股份有限公司 一种梯形图转换二叉树的方法、装置、设备及存储介质
CN112398224B (zh) * 2020-11-12 2022-09-27 山东鲁软数字科技有限公司 一种配电环网图中环网模型的整体布局方法及系统
CN113919279B (zh) * 2021-12-09 2022-04-26 深圳佑驾创新科技有限公司 高效pcb布局方法、装置、设备及计算机可读存储介质
CN116663475A (zh) * 2022-02-18 2023-08-29 长鑫存储技术有限公司 版图布局布线方法、电路版图、电子设备以及存储介质
CN116011395B (zh) * 2023-01-11 2023-12-08 上海合见工业软件集团有限公司 基于模块交换的电路示意图模块列排序方法、设备和介质
CN117151279A (zh) * 2023-08-15 2023-12-01 哈尔滨工业大学 一种基于线图神经网络的同构网络链路预测方法及系统

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2093080A5 (es) * 1970-06-01 1972-01-28 Snecma
JPH0623985B2 (ja) * 1984-02-22 1994-03-30 株式会社日立製作所 論理図自動生成方法
US4813013A (en) * 1984-03-01 1989-03-14 The Cadware Group, Ltd. Schematic diagram generating system using library of general purpose interactively selectable graphic primitives to create special applications icons
JPS60205672A (ja) * 1984-03-30 1985-10-17 Hitachi Ltd 論理回路図の論理シンボル配置方法
JPS61199166A (ja) * 1985-03-01 1986-09-03 Nec Corp 配線経路探索装置
JPS61204775A (ja) * 1985-03-07 1986-09-10 Fujitsu Ltd 回路図自動生成方法
US4914568A (en) * 1986-10-24 1990-04-03 National Instruments, Inc. Graphical system for modelling a process and associated method
JPS63225869A (ja) * 1986-10-09 1988-09-20 Nec Corp 配線経路探索方式
US4868785A (en) * 1987-01-27 1989-09-19 Tektronix, Inc. Block diagram editor system and method for controlling electronic instruments
US4852015A (en) * 1987-06-24 1989-07-25 Eta Systems, Inc. Automatic circuit layout router
JP2535976B2 (ja) * 1987-11-17 1996-09-18 株式会社日立製作所 形態接続構成自動作成システム
US4922432A (en) * 1988-01-13 1990-05-01 International Chip Corporation Knowledge based method and apparatus for designing integrated circuits using functional specifications
US5046012A (en) * 1988-06-17 1991-09-03 Fujitsu Limited Pattern data processing method

Also Published As

Publication number Publication date
JPH0275072A (ja) 1990-03-14
DE68929155T2 (de) 2000-08-24
EP0612020B1 (en) 1999-12-08
EP0612022A2 (en) 1994-08-24
ES2134895T3 (es) 1999-10-16
EP0612020A2 (en) 1994-08-24
DE68927433D1 (de) 1996-12-12
DE68929552D1 (de) 2007-07-05
ATE189543T1 (de) 2000-02-15
EP0950966A3 (en) 2001-06-20
DE68929052T2 (de) 2000-02-03
US5550714A (en) 1996-08-27
EP0950966B1 (en) 2007-05-23
KR900005323A (ko) 1990-04-14
ES2285815T3 (es) 2007-11-16
ATE193134T1 (de) 2000-06-15
DE68929110D1 (de) 2000-01-13
EP0363017B1 (en) 1996-11-06
EP0612020A3 (en) 1996-07-17
DE68929110T2 (de) 2000-04-06
KR930001025B1 (ko) 1993-02-12
EP0363017A3 (en) 1991-04-10
ATE183321T1 (de) 1999-08-15
EP0612021A3 (en) 1996-05-15
JPH0786883B2 (ja) 1995-09-20
EP0612023B1 (en) 2000-02-02
ATE145076T1 (de) 1996-11-15
DE68929212D1 (de) 2000-06-21
DE68929155D1 (de) 2000-03-09
ATE187566T1 (de) 1999-12-15
EP0612023A3 (en) 1996-09-04
ATE363103T1 (de) 2007-06-15
EP0612022A3 (en) 1996-08-07
EP0363017A2 (en) 1990-04-11
DE68929052D1 (de) 1999-09-16
EP0612022B1 (en) 1999-08-11
DE68927433T2 (de) 1997-05-28
EP0612023A2 (en) 1994-08-24
DE68929552T2 (de) 2008-01-24
EP0612021B1 (en) 2000-05-17
EP0950966A2 (en) 1999-10-20
DE68929212T2 (de) 2000-09-28
EP0612021A2 (en) 1994-08-24

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