ES2148351T3 - Procedimiento y aparato para mejorar la precision aparente de un circuito reloj receptor de datos. - Google Patents

Procedimiento y aparato para mejorar la precision aparente de un circuito reloj receptor de datos.

Info

Publication number
ES2148351T3
ES2148351T3 ES95100183T ES95100183T ES2148351T3 ES 2148351 T3 ES2148351 T3 ES 2148351T3 ES 95100183 T ES95100183 T ES 95100183T ES 95100183 T ES95100183 T ES 95100183T ES 2148351 T3 ES2148351 T3 ES 2148351T3
Authority
ES
Spain
Prior art keywords
clock circuit
timing
procedure
improve
accuracy
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
ES95100183T
Other languages
English (en)
Inventor
G Kent Walker
Paul Moroney
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Arris Technology Inc
Original Assignee
Arris Technology Inc
General Instrument Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Arris Technology Inc, General Instrument Corp filed Critical Arris Technology Inc
Application granted granted Critical
Publication of ES2148351T3 publication Critical patent/ES2148351T3/es
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/0079—Receiver details
    • H04L7/0083—Receiver details taking measures against momentary loss of synchronisation, e.g. inhibiting the synchronisation, using idle words or using redundant clocks
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/02—Details
    • H04J3/06—Synchronising arrangements
    • H04J3/062—Synchronisation of signals having the same nominal but fluctuating bit rates, e.g. using buffers
    • H04J3/0632—Synchronisation of packets and cells, e.g. transmission of voice via a packet network, circuit emulation service [CES]

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Multimedia (AREA)
  • Computer Hardware Design (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)
  • Information Transfer Systems (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
  • Circuits Of Receivers In General (AREA)
  • Two-Way Televisions, Distribution Of Moving Picture Or The Like (AREA)

Abstract

LA PRECISION APARENTE DE UN CIRCUITO DE RELOJ (20) UTILIZADA PARA PROTEGER SEÑALES DE INFORMACION TRANSMITIDAS Y TEMPORIZADAS EN UN RECEPTOR DE DATOS, ES MEJORADA. UNA RELACION DE TEMPORIZACION INHERENTE A UNA SEÑAL RECIBIDA (10) ES DETECTADA (34,40) ANTES DE LA ADQUISICION DE UN COMPONENTE TEMPORIZADOR (16) INCLUIDO EN UNA PORCION DE INFORMACION DESEADA DE LA SEÑAL RECIBIDA. LA RELACION DE TEMPORIZACION TIENE UNA PRECISION QUE ES MAYOR QUE LA PRECISION DEL CIRCUITO DE RELOJ (20). EL CIRCUITO DE RELOJ (20) SE CONTROLA EN RESPUESTA A LA RELACION DE TEMPORIZACION PARA FUNCIONAR CON MAYOR PRECISION. TRAS ELLO, EL COMPONENTE DE TEMPORIZACION INCLUIDO SE ADQUIERE Y UTILIZA PARA CONTROLAR EL CIRCUITO DE RELOJ. EN UNA EXPRESION ILUSTRADA, LA RELACION DE TEMPORIZACION SE DERIVA DE UNA PROPORCION DE SIMBOLOS (40) DE LA SEÑAL RECIBIDA. EN UNA EXPRESION ALTERNATIVA, LA RELACION DE TEMPORIZACION SE OBTIENE A PARTIR DE UNAS SEÑALES DE REFERENCIA TRANSMITIDAS SEPARADAS (34) TALES COMO SEÑALES TRANSMITIDAS DE TELEVISION.
ES95100183T 1994-02-02 1995-01-09 Procedimiento y aparato para mejorar la precision aparente de un circuito reloj receptor de datos. Expired - Lifetime ES2148351T3 (es)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US08/191,028 US5579348A (en) 1994-02-02 1994-02-02 Method and apparatus for improving the apparent accuracy of a data receiver clock circuit

Publications (1)

Publication Number Publication Date
ES2148351T3 true ES2148351T3 (es) 2000-10-16

Family

ID=22703834

Family Applications (1)

Application Number Title Priority Date Filing Date
ES95100183T Expired - Lifetime ES2148351T3 (es) 1994-02-02 1995-01-09 Procedimiento y aparato para mejorar la precision aparente de un circuito reloj receptor de datos.

Country Status (8)

Country Link
US (1) US5579348A (es)
EP (1) EP0671828B1 (es)
JP (1) JP3431717B2 (es)
KR (1) KR100356751B1 (es)
AU (1) AU679138B2 (es)
CA (1) CA2140457C (es)
DE (1) DE69517351T2 (es)
ES (1) ES2148351T3 (es)

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CA2146801C (en) * 1994-05-27 1999-11-02 Barin Geoffry Haskell Timing recovery for variable bit-rate video on asynchronous transfer mode (atm) networks
EP0876017A1 (en) * 1997-05-02 1998-11-04 Lsi Logic Corporation Digital clock recovery
US6298088B1 (en) * 1997-05-28 2001-10-02 Sarnoff Corporation Method and apparatus for splicing compressed information signals
JP2002271307A (ja) * 2001-03-09 2002-09-20 Sega Corp 端末同期方法、通信システム及び端末装置
US6829014B1 (en) * 2001-05-04 2004-12-07 General Instrument Corporation Frequency bounded oscillator for video reconstruction
US7372875B2 (en) * 2002-09-30 2008-05-13 Lucent Technologies Inc. Systems and methods for synchronization in asynchronous transport networks
US7064617B2 (en) * 2003-05-02 2006-06-20 Silicon Laboratories Inc. Method and apparatus for temperature compensation
US7436227B2 (en) * 2003-05-02 2008-10-14 Silicon Laboratories Inc. Dual loop architecture useful for a programmable clock source and clock multiplier applications
US7187241B2 (en) * 2003-05-02 2007-03-06 Silicon Laboratories Inc. Calibration of oscillator devices
US7288998B2 (en) * 2003-05-02 2007-10-30 Silicon Laboratories Inc. Voltage controlled clock synthesizer
US7295077B2 (en) * 2003-05-02 2007-11-13 Silicon Laboratories Inc. Multi-frequency clock synthesizer
US7456765B1 (en) * 2004-05-25 2008-11-25 Cirrus Logic, Inc. Systems and methods for clock mode determination utilizing master clock frequency measurements
US8326075B2 (en) * 2008-09-11 2012-12-04 Google Inc. System and method for video encoding using adaptive loop filter
US20120223849A1 (en) * 2011-03-03 2012-09-06 Exar Corporation Set-point resolution improvement for switch mode power supplies
US8780971B1 (en) 2011-04-07 2014-07-15 Google, Inc. System and method of encoding using selectable loop filters
US8780996B2 (en) 2011-04-07 2014-07-15 Google, Inc. System and method for encoding and decoding video data
US8781004B1 (en) 2011-04-07 2014-07-15 Google Inc. System and method for encoding video using variable loop filter
US8885706B2 (en) 2011-09-16 2014-11-11 Google Inc. Apparatus and methodology for a video codec system with noise reduction capability
US9131073B1 (en) 2012-03-02 2015-09-08 Google Inc. Motion estimation aided noise reduction
US9344729B1 (en) 2012-07-11 2016-05-17 Google Inc. Selective prediction signal filtering
US9523763B2 (en) * 2013-03-03 2016-12-20 The Boeing Company Satellite-based integer cycle ambiguity resolution of local medium wave radio signals
JP6149594B2 (ja) * 2013-08-09 2017-06-21 富士通株式会社 受信回路
US10102613B2 (en) 2014-09-25 2018-10-16 Google Llc Frequency-domain denoising
US10615954B2 (en) * 2015-03-24 2020-04-07 Maxlinear, Inc. Low-power asynchronous data links

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Publication number Priority date Publication date Assignee Title
BE791484A (nl) * 1971-11-18 1973-05-16 Trt Telecom Radio Electr Systeem voor synchrone datatransmissie over een synchroon digitaal transmissiekanaal
US3806822A (en) * 1972-12-13 1974-04-23 Motorola Inc Phase locked loop employing gated alternating current injection for fast synchronization
US4017803A (en) * 1976-01-29 1977-04-12 Sperry Rand Corporation Data recovery system resistant to frequency deviations
US4077016A (en) * 1977-02-22 1978-02-28 Ncr Corporation Apparatus and method for inhibiting false locking of a phase-locked loop
KR900000464B1 (ko) * 1984-10-05 1990-01-30 가부시기가이샤 히다찌세이사꾸쇼 복조 회로
US4633193A (en) * 1985-12-02 1986-12-30 At&T Bell Laboratories Clock circuit synchronizer using a frequency synthesizer controlled by a frequency estimator
GB2223136B (en) * 1988-03-28 1992-10-14 Plessey Co Plc Broad band vco control system for clock recovery
US4893319A (en) * 1988-12-19 1990-01-09 Planar Systems, Inc. Clock regeneration circuit employing digital phase locked loop
US5276716A (en) * 1990-02-15 1994-01-04 Advanced Micro Devices Inc. Bi-phase decoder phase-lock loop in CMOS
US5184091A (en) * 1991-06-04 1993-02-02 Zenith Electronics Corporation Circuit for phase locking an oscillator within any one of a plurality of frequency ranges
US5241382A (en) * 1992-04-25 1993-08-31 General Instrument Corporation Digital HDTV data packet format and receiver therefor
US5231486A (en) * 1992-07-27 1993-07-27 General Electric Company Data separation processing in a dual channel digital high definition television system

Also Published As

Publication number Publication date
AU679138B2 (en) 1997-06-19
US5579348A (en) 1996-11-26
CA2140457A1 (en) 1995-08-03
EP0671828B1 (en) 2000-06-07
AU1026295A (en) 1995-08-10
EP0671828A1 (en) 1995-09-13
CA2140457C (en) 2000-08-08
KR100356751B1 (ko) 2003-01-10
DE69517351T2 (de) 2001-01-25
JP3431717B2 (ja) 2003-07-28
KR950035186A (ko) 1995-12-30
JPH08102731A (ja) 1996-04-16
DE69517351D1 (de) 2000-07-13

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