ES2154269T3 - Sistema de procesamiento en tiempo real. - Google Patents

Sistema de procesamiento en tiempo real.

Info

Publication number
ES2154269T3
ES2154269T3 ES93908603T ES93908603T ES2154269T3 ES 2154269 T3 ES2154269 T3 ES 2154269T3 ES 93908603 T ES93908603 T ES 93908603T ES 93908603 T ES93908603 T ES 93908603T ES 2154269 T3 ES2154269 T3 ES 2154269T3
Authority
ES
Spain
Prior art keywords
bus
memory
port
processing system
writing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
ES93908603T
Other languages
English (en)
Inventor
Anil Gupta
Walter Nixon
Hugh Humphreys
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sun Microsystems Inc
Original Assignee
Sun Microsystems Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sun Microsystems Inc filed Critical Sun Microsystems Inc
Application granted granted Critical
Publication of ES2154269T3 publication Critical patent/ES2154269T3/es
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G06F15/163—Interprocessor communication
    • G06F15/17—Interprocessor communication using an input/output type connection, e.g. channel, I/O port

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Theoretical Computer Science (AREA)
  • Software Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Multi Processors (AREA)
  • Computer And Data Communications (AREA)

Abstract

SE PRESENTA UN SISTEMA DE PROCESAMIENTO DE DATOS EN TIEMPO REAL QUE CONSTA DE UNA PLURALIDAD DE NODOS DE PROCESAMIENTO (NODO1, NODO2, NODO3) Y UN ENLACE DE DATOS DE SOLO ESCRITURA (46) PARA TRANSFERIR LA INFORMACION QUE CONTIENE LA ESCRITURA SOLAMENTE ENTRE LA PLURALIDAD DE NODOS DE PROCESAMIENTO. TODOS LOS NODOS (NODO1, NODO2, NODO3) INCLUYEN UN BUS (22), UN PROCESADOR (20) ACOPLADOS AL BUS (22), UNA MEMORIA (40) QUE TIENE AL MENOS DOS PUERTOS CON UN PUERTO (42) CONECTADO AL BUS Y EL OTRO PUERTO (48) CONECTADO AL ENLACE DE DATOS (46) Y UN SENSOR (60) PARA MEDIR UNA ESCRITURA EN LA MEMORIA (40). AL MENOS UN NODO TIENE UN BUS VME (22) COMO EL BUS (22) Y SIRVE COMO UNA ENTRADA/SALIDA CONECTADA A UN PUERTO (42) DE LA MEMORIA (40). SE INCLUYE UN BUS LOCAL ADICIONAL (24) PARA INTRODUCIR Y HACER SALIR LOS DATOS DE LA MEMORIA (40). EL BUS LOCAL (24) ESTA CONECTADO A UN TERCER PUERTO (44) DE LA MEMORIA (40).
ES93908603T 1992-03-25 1993-03-25 Sistema de procesamiento en tiempo real. Expired - Lifetime ES2154269T3 (es)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US85758092A 1992-03-25 1992-03-25

Publications (1)

Publication Number Publication Date
ES2154269T3 true ES2154269T3 (es) 2001-04-01

Family

ID=25326307

Family Applications (1)

Application Number Title Priority Date Filing Date
ES93908603T Expired - Lifetime ES2154269T3 (es) 1992-03-25 1993-03-25 Sistema de procesamiento en tiempo real.

Country Status (8)

Country Link
US (1) US5475858A (es)
EP (1) EP0632912B1 (es)
JP (1) JP2677454B2 (es)
AU (1) AU3936593A (es)
CA (1) CA2129825C (es)
DE (1) DE69329904T2 (es)
ES (1) ES2154269T3 (es)
WO (1) WO1993019421A1 (es)

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US5708850A (en) * 1994-07-27 1998-01-13 Sony Corporation Parallel processing system for time division multiplex data transfer including read/write dual port memory accessible to bus and digital signal processor during opposite phases of clock
US6295585B1 (en) * 1995-06-07 2001-09-25 Compaq Computer Corporation High-performance communication method and apparatus for write-only networks
US5742845A (en) 1995-06-22 1998-04-21 Datascape, Inc. System for extending present open network communication protocols to communicate with non-standard I/O devices directly coupled to an open network
KR0154618B1 (ko) * 1995-11-01 1998-11-16 양승택 브이엠이 버스의 양포트 램 정합회로
US5719860A (en) * 1996-03-22 1998-02-17 Tellabs Wireless, Inc. Wideband bus for wireless base station
US5970510A (en) * 1996-04-10 1999-10-19 Northrop Grumman Corporation Distributed memory addressing system
US5946711A (en) * 1997-05-30 1999-08-31 Oracle Corporation System for locking data in a shared cache
US6574720B1 (en) 1997-05-30 2003-06-03 Oracle International Corporation System for maintaining a buffer pool
US6324623B1 (en) 1997-05-30 2001-11-27 Oracle Corporation Computing system for implementing a shared cache
US6078994A (en) * 1997-05-30 2000-06-20 Oracle Corporation System for maintaining a shared cache in a multi-threaded computer environment
US6295584B1 (en) * 1997-08-29 2001-09-25 International Business Machines Corporation Multiprocessor computer system with memory map translation
US5970232A (en) * 1997-11-17 1999-10-19 Cray Research, Inc. Router table lookup mechanism
US6101181A (en) * 1997-11-17 2000-08-08 Cray Research Inc. Virtual channel assignment in large torus systems
US6230252B1 (en) 1997-11-17 2001-05-08 Silicon Graphics, Inc. Hybrid hypercube/torus architecture
US6085303A (en) * 1997-11-17 2000-07-04 Cray Research, Inc. Seralized race-free virtual barrier network
US6393530B1 (en) 1998-04-17 2002-05-21 Intelect Communications, Inc. Paging method for DSP
US6678801B1 (en) * 1998-04-17 2004-01-13 Terraforce Technologies Corp. DSP with distributed RAM structure
US6456628B1 (en) * 1998-04-17 2002-09-24 Intelect Communications, Inc. DSP intercommunication network
US6163829A (en) * 1998-04-17 2000-12-19 Intelect Systems Corporation DSP interrupt control for handling multiple interrupts
US6216174B1 (en) 1998-09-29 2001-04-10 Silicon Graphics, Inc. System and method for fast barrier synchronization
DE10081049D2 (de) * 1999-04-20 2001-08-09 Siemens Ag Skalierbares Multi-Prozessorsystem für Echtzeitanwendungen in der Nachrichtentechnik
US6311255B1 (en) * 1999-04-29 2001-10-30 International Business Machines Corporation System and method for selectively restricting access to memory for bus attached unit IDs
US6674720B1 (en) 1999-09-29 2004-01-06 Silicon Graphics, Inc. Age-based network arbitration system and method
US6751698B1 (en) 1999-09-29 2004-06-15 Silicon Graphics, Inc. Multiprocessor node controller circuit and method
US6542949B1 (en) 1999-11-08 2003-04-01 International Business Machines Corporation Method and apparatus for increased performance of a parked data bus in the non-parked direction
US6889278B1 (en) * 2001-04-04 2005-05-03 Cisco Technology, Inc. Method and apparatus for fast acknowledgement and efficient servicing of interrupt sources coupled to high latency paths
US7010740B1 (en) * 2001-05-17 2006-03-07 Emc Corporation Data storage system having no-operation command
US6920485B2 (en) * 2001-10-04 2005-07-19 Hewlett-Packard Development Company, L.P. Packet processing in shared memory multi-computer systems
US20030069949A1 (en) * 2001-10-04 2003-04-10 Chan Michele W. Managing distributed network infrastructure services
US6999998B2 (en) * 2001-10-04 2006-02-14 Hewlett-Packard Development Company, L.P. Shared memory coupling of network infrastructure devices
US7315551B2 (en) * 2002-03-15 2008-01-01 Lockheed Martin Corporation Synchronous low voltage differential I/O buss
US20030185177A1 (en) * 2002-03-26 2003-10-02 Interdigital Technology Corporation TDD-RLAN wireless telecommunication system with RAN IP gateway and methods
US20060083102A1 (en) * 2004-10-20 2006-04-20 Seagate Technology Llc Failover control of dual controllers in a redundant data storage system
US20060294300A1 (en) * 2005-06-22 2006-12-28 Seagate Technology Llc Atomic cache transactions in a distributed storage system
US12321300B2 (en) * 2023-06-30 2025-06-03 Advanced Micro Devices, Inc. Apparatus and methods for translating transactions between one or more requesting units and a target unit

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FR2472234A1 (fr) * 1979-12-21 1981-06-26 Philips Ind Commerciale Protocoles de communication geres par les modules de communication utilises dans un systeme de traitement de donnees reparti
US4363093A (en) * 1980-03-10 1982-12-07 International Business Machines Corporation Processor intercommunication system
US4394726A (en) * 1981-04-29 1983-07-19 The United States Of America As Represented By The Administrator Of The National Aeronautics And Space Administration Distributed multiport memory architecture
GB2156554B (en) * 1984-03-10 1987-07-29 Rediffusion Simulation Ltd Processing system with shared data
US4604683A (en) * 1984-12-10 1986-08-05 Advanced Computer Communications Communication controller using multiported random access memory
US5146607A (en) * 1986-06-30 1992-09-08 Encore Computer Corporation Method and apparatus for sharing information between a plurality of processing units
DE3788826T2 (de) * 1986-06-30 1994-05-19 Encore Computer Corp Verfahren und Vorrichtung zur gemeinsamen Informationsbenutzung zwischen einer Mehrzahl von Verarbeitungseinheiten.
US4833625A (en) * 1986-07-09 1989-05-23 University Of Arizona Image viewing station for picture archiving and communications systems (PACS)
US4914570A (en) * 1986-09-15 1990-04-03 Counterpoint Computers, Inc. Process distribution and sharing system for multiple processor computer system
US5010515A (en) * 1987-07-28 1991-04-23 Raster Technologies, Inc. Parallel graphics processor with workload distributing and dependency mechanisms and method for distributing workload
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US5237670A (en) * 1989-01-30 1993-08-17 Alantec, Inc. Method and apparatus for data transfer between source and destination modules
IT1228728B (it) * 1989-03-15 1991-07-03 Bull Hn Information Syst Sistema multiprocessore con replicazione di dati globali e due livelli di unita' di traduzione indirizzi.

Also Published As

Publication number Publication date
EP0632912A1 (en) 1995-01-11
WO1993019421A1 (en) 1993-09-30
US5475858A (en) 1995-12-12
CA2129825C (en) 2000-08-15
JP2677454B2 (ja) 1997-11-17
DE69329904T2 (de) 2001-06-13
DE69329904D1 (de) 2001-03-08
JPH07504774A (ja) 1995-05-25
CA2129825A1 (en) 1993-09-30
AU3936593A (en) 1993-10-21
EP0632912A4 (en) 1998-06-03
EP0632912B1 (en) 2001-01-31

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