ES2157666T3 - Circuito para la activacion de una disposicion de memoria de semiconductores no volatil. - Google Patents

Circuito para la activacion de una disposicion de memoria de semiconductores no volatil.

Info

Publication number
ES2157666T3
ES2157666T3 ES98936116T ES98936116T ES2157666T3 ES 2157666 T3 ES2157666 T3 ES 2157666T3 ES 98936116 T ES98936116 T ES 98936116T ES 98936116 T ES98936116 T ES 98936116T ES 2157666 T3 ES2157666 T3 ES 2157666T3
Authority
ES
Spain
Prior art keywords
circuit
data
semiconductor memory
input
nmos transistor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
ES98936116T
Other languages
English (en)
Inventor
Thomas Zettler
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Infineon Technologies AG
Original Assignee
Infineon Technologies AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Infineon Technologies AG filed Critical Infineon Technologies AG
Application granted granted Critical
Publication of ES2157666T3 publication Critical patent/ES2157666T3/es
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits

Landscapes

  • Read Only Memory (AREA)
  • Static Random-Access Memory (AREA)
  • Non-Volatile Memory (AREA)
  • Semiconductor Memories (AREA)

Abstract

Circuito para la activación de una disposición de memoria de semiconductores no volátil, con un circuito de conversión de nivel (10), que aplica un valor de salida (D) y un valor de salida (DN) complementario de este valor de salida, a una línea de bits y/o a una línea de palabra de la disposición de memoria de semiconductores, con un circuito de bloqueo (enganche) (11) que se encuentra entre un circuito de entrada (12) y el circuito de conversión de nivel (10), y que memoriza temporalmente los datos a memorizar en la disposición de memoria de semiconductores, caracterizado porque el circuito de entrada (12) consta de un primer transistor NMOS (N1) que se encuentra con su trayectoria de fuente-drenaje dispuesta entre una entrada de datos (DATA) y una primera salida de datos conectada a una entrada de control del circuito de conversión de nivel (10), y de un circuito en serie que consta de dos segundos y terceros transistores NMOS (N2, N3) que se encuentran entre toma de tierra y una segundasalida de datos, que está conectada a una conexión de control del circuito de conversión de nivel (10), y que es complementaria de la conexión de control, estando conectada la puerta del segundo transistor NMOS (N2) a la puerta del primer transistor NMOS (N1) y estando conectada la puerta del tercer transistor NMOS (N3) a la entrada de datos (DATA).
ES98936116T 1997-06-13 1998-06-08 Circuito para la activacion de una disposicion de memoria de semiconductores no volatil. Expired - Lifetime ES2157666T3 (es)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
DE19725181A DE19725181A1 (de) 1997-06-13 1997-06-13 Ansteuerschaltung für nichtflüchtige Halbleiter-Speicheranordnung

Publications (1)

Publication Number Publication Date
ES2157666T3 true ES2157666T3 (es) 2001-08-16

Family

ID=7832475

Family Applications (1)

Application Number Title Priority Date Filing Date
ES98936116T Expired - Lifetime ES2157666T3 (es) 1997-06-13 1998-06-08 Circuito para la activacion de una disposicion de memoria de semiconductores no volatil.

Country Status (12)

Country Link
US (1) US6137315A (es)
EP (1) EP0988633B1 (es)
JP (1) JP3399547B2 (es)
KR (1) KR20010013737A (es)
CN (1) CN1124617C (es)
AT (1) ATE201112T1 (es)
BR (1) BR9810100A (es)
DE (2) DE19725181A1 (es)
ES (1) ES2157666T3 (es)
RU (1) RU2221286C2 (es)
UA (1) UA42887C2 (es)
WO (1) WO1998058384A1 (es)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE19921868C2 (de) * 1999-05-11 2001-03-15 Siemens Ag Schaltungsanordnung zur Kontrolle von Zuständen einer Speichereinrichtung
US7440311B2 (en) * 2006-09-28 2008-10-21 Novelics, Llc Single-poly non-volatile memory cell
US7554860B1 (en) 2007-09-21 2009-06-30 Actel Corporation Nonvolatile memory integrated circuit having assembly buffer and bit-line driver, and method of operation thereof
RU2438194C1 (ru) * 2007-12-28 2011-12-27 Шарп Кабусики Кайся Схема управления линии запоминающего конденсатора и устройство отображения
US8718223B2 (en) 2007-12-28 2014-05-06 Sharp Kabushiki Kaisha Semiconductor device and display device
CN103036548B (zh) 2007-12-28 2016-01-06 夏普株式会社 半导体装置和显示装置
US8547368B2 (en) 2007-12-28 2013-10-01 Sharp Kabushiki Kaisha Display driving circuit having a memory circuit, display device, and display driving method

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4599707A (en) * 1984-03-01 1986-07-08 Signetics Corporation Byte wide EEPROM with individual write circuits and write prevention means
US4716312A (en) * 1985-05-07 1987-12-29 California Institute Of Technology CMOS logic circuit
US4654547A (en) * 1985-06-28 1987-03-31 Itt Corporation Balanced enhancement/depletion mode gallium arsenide buffer/comparator circuit
FR2604554B1 (fr) * 1986-09-30 1988-11-10 Eurotechnique Sa Dispositif de securite pourla programmation d'une memoire non volatile programmable electriquement
JP2773786B2 (ja) * 1991-02-15 1998-07-09 日本電気アイシーマイコンシステム株式会社 書き込み電圧発生回路
JP3173247B2 (ja) * 1993-09-29 2001-06-04 ソニー株式会社 レベルシフタ
US5682345A (en) * 1995-07-28 1997-10-28 Micron Quantum Devices, Inc. Non-volatile data storage unit method of controlling same
JP3404712B2 (ja) * 1996-05-15 2003-05-12 株式会社東芝 不揮発性半導体記憶装置及びその書き込み方法

Also Published As

Publication number Publication date
UA42887C2 (uk) 2001-11-15
DE59800692D1 (de) 2001-06-13
CN1260901A (zh) 2000-07-19
EP0988633A1 (de) 2000-03-29
EP0988633B1 (de) 2001-05-09
JP3399547B2 (ja) 2003-04-21
WO1998058384A1 (de) 1998-12-23
US6137315A (en) 2000-10-24
CN1124617C (zh) 2003-10-15
BR9810100A (pt) 2000-08-08
DE19725181A1 (de) 1999-02-25
ATE201112T1 (de) 2001-05-15
RU2221286C2 (ru) 2004-01-10
KR20010013737A (ko) 2001-02-26
JP2001505350A (ja) 2001-04-17

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