ES2170590T3 - Dispositivo de procesamiento digital. - Google Patents

Dispositivo de procesamiento digital.

Info

Publication number
ES2170590T3
ES2170590T3 ES99951270T ES99951270T ES2170590T3 ES 2170590 T3 ES2170590 T3 ES 2170590T3 ES 99951270 T ES99951270 T ES 99951270T ES 99951270 T ES99951270 T ES 99951270T ES 2170590 T3 ES2170590 T3 ES 2170590T3
Authority
ES
Spain
Prior art keywords
circuits
level
circuit
tree
processing device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
ES99951270T
Other languages
English (en)
Inventor
Arne Halaas
Borge Svingen
Geirr I Leistad
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fast Search and Transfer AS
Original Assignee
Fast Search and Transfer AS
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fast Search and Transfer AS filed Critical Fast Search and Transfer AS
Application granted granted Critical
Publication of ES2170590T3 publication Critical patent/ES2170590T3/es
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G06F15/163—Interprocessor communication
    • G06F15/173—Interprocessor communication using an interconnection network, e.g. matrix, shuffle, pyramid, star, snowflake
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G06F15/163—Interprocessor communication
    • G06F15/173—Interprocessor communication using an interconnection network, e.g. matrix, shuffle, pyramid, star, snowflake
    • G06F15/17337—Direct connection machines, e.g. completely connected computers, point to point communication networks
    • G06F15/17343—Direct connection machines, e.g. completely connected computers, point to point communication networks wherein the interconnection is dynamically configurable, e.g. having loosely coupled nearest neighbor architecture
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/80—Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors
    • G06F15/8007—Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors single instruction multiple data [SIMD] multiprocessors
    • G06F15/8023—Two dimensional arrays, e.g. mesh, torus

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Mathematical Physics (AREA)
  • Software Systems (AREA)
  • Computing Systems (AREA)
  • Multi Processors (AREA)
  • Communication Control (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Debugging And Monitoring (AREA)
  • Image Processing (AREA)
  • Complex Calculations (AREA)
  • Mobile Radio Communication Systems (AREA)
  • Bidet-Like Cleaning Device And Other Flush Toilet Accessories (AREA)
  • Logic Circuits (AREA)
  • Bridges Or Land Bridges (AREA)
  • Exchange Systems With Centralized Control (AREA)

Abstract

Un dispositivo de procesamiento digital P, particularmente para procesar datos digitales y estructuras de señales, en que las estructuras de datos y señales comprenden secuencias repetidas y/o patrones anidados, y en que el dispositivo de procesamiento P generalmente está configurado como un árbol normal con n+1 niveles So, S1, ... Sn y degradok,caracterizado porque el dispositivo de procesamiento P está provisto en la forma de un circuito Pn en el nivel Sn, y que forma el nodo raíz del árbol, en que el nivel más próximo Sn-1 está provisto en forma anidada en el circuito Pn, y que comprende k circuitos Pn-1 que forman los nodos hijo del nodo raíz, en que generalmente un nivel subyaciente Sn-q en el circuito Pn, en donde q 2 f1, 2 .. n-1g, comprende k q circuitos Pn-q provistos en forma anidada en los k q-1 circuitos Pn-q+1 en el nivel solapante Sn-q+1, en que cada circuito Pn-q+1 en este nivel comprende k circuitos Pn-q, en que el nivel cero definido Sn-q = So en el circuito Pn para q = n comprende de k n-1 +1 a k n circuitos Po, los cuales constituyen los procesadores de núcleos en el dispositivo de procesado P, y que sobre este nivel So forman los nodos de hojas en el árbol, estando provisto el procesador de núcleo Po anidado en un número de 1 a k, en cada uno de los k n-1 circuitos P1 en el nivel S1, en que cada uno de los circuitos P1, P2 ... Pn en los niveles respectivos S1, S2, ...Sn comprenden una unidad lógica E que generalmente está conectada con dichos circuitos Po, P1, ... Pn-1 en el nivel subyacente respectivo más próximo So, S1 ... Sn-1 que se proporcionan anidados en los circuitos respectivos P1, P2, ... Pn, y de acuerdo con la selección que configura una red de los circuitos anteriores en los circuitos respectivos P1, P2, ... Pn , y en que cada uno de los circuitos Po, P1 ... Pn tienen interfaces idénticas I.
ES99951270T 1998-10-09 1999-10-08 Dispositivo de procesamiento digital. Expired - Lifetime ES2170590T3 (es)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
NO984746A NO984746D0 (no) 1998-10-09 1998-10-09 Digital prosesseringsenhet

Publications (1)

Publication Number Publication Date
ES2170590T3 true ES2170590T3 (es) 2002-08-01

Family

ID=19902501

Family Applications (1)

Application Number Title Priority Date Filing Date
ES99951270T Expired - Lifetime ES2170590T3 (es) 1998-10-09 1999-10-08 Dispositivo de procesamiento digital.

Country Status (17)

Country Link
US (1) US6760744B1 (es)
EP (1) EP1125216B1 (es)
JP (1) JP3789302B2 (es)
KR (1) KR100373426B1 (es)
CN (1) CN1120434C (es)
AT (1) ATE211838T1 (es)
AU (1) AU750622B2 (es)
BR (1) BR9914318A (es)
CA (1) CA2344149C (es)
DE (1) DE69900796T2 (es)
DK (1) DK1125216T3 (es)
ES (1) ES2170590T3 (es)
HK (1) HK1042570B (es)
IL (1) IL142001A0 (es)
NO (1) NO984746D0 (es)
PT (1) PT1125216E (es)
WO (1) WO2000022545A2 (es)

Families Citing this family (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6940998B2 (en) 2000-02-04 2005-09-06 Cernium, Inc. System for automated screening of security cameras
US6957318B2 (en) * 2001-08-17 2005-10-18 Sun Microsystems, Inc. Method and apparatus for controlling a massively parallel processing environment
US7664840B2 (en) * 2001-09-13 2010-02-16 Network Foundation Technologies, Llc Systems for distributing data over a computer network and methods for arranging nodes for distribution of data over a computer network
FR2836731B1 (fr) * 2002-03-01 2004-12-03 Abdulai Danso Procede pour la realisation et la mise en oeuvre d'un systeme de communication multifonctionnel et systeme obtenu conformement audit procede
US20030177166A1 (en) * 2002-03-15 2003-09-18 Research Foundation Of The State University Of New York Scalable scheduling in parallel processors
US7822224B2 (en) * 2005-06-22 2010-10-26 Cernium Corporation Terrain map summary elements
EP1808774A1 (en) * 2005-12-22 2007-07-18 St Microelectronics S.A. A hierarchical reconfigurable computer architecture
US7801901B2 (en) * 2006-09-15 2010-09-21 Microsoft Corporation Tracking storylines around a query
US8150889B1 (en) * 2008-08-28 2012-04-03 Amazon Technologies, Inc. Parallel processing framework
US8571261B2 (en) 2009-04-22 2013-10-29 Checkvideo Llc System and method for motion detection in a surveillance video
GB201904267D0 (en) * 2019-03-27 2019-05-08 Graphcore Ltd A networked computer with multiple embedded rings
US10956357B2 (en) * 2019-04-01 2021-03-23 International Business Machines Corporation Method for flexible, fast all-reduce on arbitrary tree topology
US12444190B2 (en) 2020-11-30 2025-10-14 Getac Technology Corporation Artificial intelligence (AI) trained data model selection
US11271810B1 (en) 2020-11-30 2022-03-08 Getac Technology Corporation Heterogeneous cross-cloud service interoperability
US11605288B2 (en) 2020-11-30 2023-03-14 Whp Workflow Solutions, Inc. Network operating center (NOC) workspace interoperability
US11630677B2 (en) 2020-11-30 2023-04-18 Whp Workflow Solutions, Inc. Data aggregation with self-configuring drivers
US11720414B2 (en) * 2020-11-30 2023-08-08 Whp Workflow Solutions, Inc. Parallel execution controller for partitioned segments of a data model
US11604773B2 (en) 2020-11-30 2023-03-14 Whp Workflow Solutions, Inc. Hierarchical data ingestion in a universal schema
US11977993B2 (en) 2020-11-30 2024-05-07 Getac Technology Corporation Data source correlation techniques for machine learning and convolutional neural models
US11540027B2 (en) 2020-11-30 2022-12-27 Getac Technology Corporation Performant ad hoc data ingestion
US11468671B2 (en) 2020-11-30 2022-10-11 Getac Technology Corporation Sentiment analysis for situational awareness
US11477616B2 (en) 2020-11-30 2022-10-18 Getac Technology Corporation Safety detection controller
US12405933B2 (en) 2020-11-30 2025-09-02 Getac Technology Corporation Content management system for trained machine learning models

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4251861A (en) 1978-10-27 1981-02-17 Mago Gyula A Cellular network of processors
US4860201A (en) 1986-09-02 1989-08-22 The Trustees Of Columbia University In The City Of New York Binary tree parallel processor
US5561768A (en) 1992-03-17 1996-10-01 Thinking Machines Corporation System and method for partitioning a massively parallel computer system
US6052712A (en) * 1996-04-30 2000-04-18 International Business Machines Corporation System for barrier synchronization wherein members dynamic voting controls the number of synchronization phases of protocols and progression to each subsequent phase
US5884046A (en) * 1996-10-23 1999-03-16 Pluris, Inc. Apparatus and method for sharing data and routing messages between a plurality of workstations in a local area network

Also Published As

Publication number Publication date
PT1125216E (pt) 2002-04-29
DE69900796T2 (de) 2002-08-22
JP3789302B2 (ja) 2006-06-21
ATE211838T1 (de) 2002-01-15
EP1125216B1 (en) 2002-01-09
CA2344149C (en) 2003-08-26
DK1125216T3 (da) 2002-04-29
CN1120434C (zh) 2003-09-03
KR100373426B1 (ko) 2003-02-25
EP1125216A2 (en) 2001-08-22
WO2000022545A3 (en) 2000-08-03
WO2000022545A2 (en) 2000-04-20
HK1042570B (zh) 2004-05-07
HK1042570A1 (en) 2002-08-16
NO984746D0 (no) 1998-10-09
AU6373999A (en) 2000-05-01
KR20010080076A (ko) 2001-08-22
CA2344149A1 (en) 2000-04-20
IL142001A0 (en) 2002-03-10
BR9914318A (pt) 2001-08-07
CN1332874A (zh) 2002-01-23
DE69900796D1 (de) 2002-02-28
US6760744B1 (en) 2004-07-06
AU750622B2 (en) 2002-07-25
JP2002527827A (ja) 2002-08-27

Similar Documents

Publication Publication Date Title
ES2170590T3 (es) Dispositivo de procesamiento digital.
EP4398114A3 (en) Scalable system on a chip
SE9902462D0 (sv) Method and apparatus in a telecommunications system
BG101797A (bg) Система за управление на взаимодействие,контролирана с интегрална схема
KR920020315A (ko) 병렬프로세서
KR860004352A (ko) 입출력처리용 연산장치
KR920015910A (ko) 연산회로
ES2122574T3 (es) Archivado de datos en memoria.
BRPI0413122A (pt) toleráncia de falha dinamicamente configurável em computação autÈnoma com múltiplos pontos de serviço
DE68926557D1 (de) Fuzzy Computersystem
KR850002906A (ko) 다중 데이타 통로 중앙 처리 유니트 구조
CA2350468A1 (en) A processing circuit and a search processor circuit
DE60004197D1 (de) Packetumleiteinrichtung
DE69518145D1 (de) Verzeichnis für ein-/ausgangsdecoder
KR900018810A (ko) 프로세서 유니트 네트워크
WO2003005225A3 (en) Processor cluster
GB2374960A (en) Causality-based memory access ordering in a multiprocessing environment
KR910015932A (ko) 멀티 프로세서 시스템의 통신관리로직
DE60003150D1 (de) Überwachungssystem
KR970002614A (ko) 프로그램 카운터 데이타를 이용한 오동작 방지회로
KR910021042A (ko) 타이머 시스템
KR910010936A (ko) 복수 프로세서간 데이타 통신 방식
KR920019093A (ko) 바이씨모스 로직의 다중 입력 낸드회로
KR950020207A (ko) 다중 프로세서의 통신장치
KR970016982A (ko) 오토리셋이 가능한 인터럽트 제어회로

Legal Events

Date Code Title Description
FG2A Definitive protection

Ref document number: 1125216

Country of ref document: ES