ES2177871T3 - Procedimiento para la verificacion de un programa, que esta presente en un lenguaje para controles programables con memoria, a traves de un ordenador. - Google Patents

Procedimiento para la verificacion de un programa, que esta presente en un lenguaje para controles programables con memoria, a traves de un ordenador.

Info

Publication number
ES2177871T3
ES2177871T3 ES97115369T ES97115369T ES2177871T3 ES 2177871 T3 ES2177871 T3 ES 2177871T3 ES 97115369 T ES97115369 T ES 97115369T ES 97115369 T ES97115369 T ES 97115369T ES 2177871 T3 ES2177871 T3 ES 2177871T3
Authority
ES
Spain
Prior art keywords
verification
program
language
procedure
computer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
ES97115369T
Other languages
English (en)
Inventor
Peter Dr Rer Nat Warkentin
Michael Dr Rer Nat Payer
Markus Holzlein
Thomas Dr Rer Nat Filkorn
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Siemens AG
Siemens Corp
Original Assignee
Siemens AG
Siemens Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siemens AG, Siemens Corp filed Critical Siemens AG
Application granted granted Critical
Publication of ES2177871T3 publication Critical patent/ES2177871T3/es
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/36—Prevention of errors by analysis, debugging or testing of software
    • G06F11/3604—Analysis of software for verifying properties of programs
    • G06F11/3608—Analysis of software for verifying properties of programs using formal methods, e.g. model checking, abstract interpretation

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Software Systems (AREA)
  • Computer Hardware Design (AREA)
  • Quality & Reliability (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Debugging And Monitoring (AREA)
  • Programmable Controllers (AREA)
  • Stored Programmes (AREA)
  • Logic Circuits (AREA)

Abstract

PARA LA VERIFICACION DE UN PROGRAMA DE SPS, ESTE SE REPRODUCE EN UN AUTOMATA FINITO (701). EL AUTOMATA FINITO SE DESCRIBE CON UN DIAGRAMA DE DECISION BINARIO (702). UNA PROPIEDAD A VERIFICAR DEL PROGRAMA DE SPS, QUE EXISTE DESCRITO EN UN LENGUAJE FORMAL DE ESPECIFICACION, SE PRUEBA MEDIANTE LA UTILIZACION DE UNA COMPROBACION SIMBOLICA DEL MODELO.
ES97115369T 1996-09-05 1997-09-04 Procedimiento para la verificacion de un programa, que esta presente en un lenguaje para controles programables con memoria, a traves de un ordenador. Expired - Lifetime ES2177871T3 (es)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
DE19636072 1996-09-05

Publications (1)

Publication Number Publication Date
ES2177871T3 true ES2177871T3 (es) 2002-12-16

Family

ID=7804727

Family Applications (1)

Application Number Title Priority Date Filing Date
ES97115369T Expired - Lifetime ES2177871T3 (es) 1996-09-05 1997-09-04 Procedimiento para la verificacion de un programa, que esta presente en un lenguaje para controles programables con memoria, a traves de un ordenador.

Country Status (4)

Country Link
EP (1) EP0828215B1 (es)
AT (1) ATE217714T1 (es)
DE (1) DE59707264D1 (es)
ES (1) ES2177871T3 (es)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE59805802D1 (de) * 1997-03-11 2002-11-07 Siemens Ag Verfahren zur rechnergestützten fehleranalyse von sensoren und/oder aktoren in einem technischen system
US6665650B1 (en) * 2000-06-15 2003-12-16 Agilent Technologies, Inc. Intelligent logic activity resolution
WO2002021344A2 (de) * 2000-09-05 2002-03-14 Infineon Technologies Ag Verfahren und anordnung zum vergleich technischer systeme unter verwendung von systemersetzungen
EP3889703B1 (en) * 2020-03-31 2023-02-01 Mitsubishi Electric R&D Centre Europe B.V. Method and apparatus for expressing and verifying functional specifications of a programmable logic controller program

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5481717A (en) * 1993-04-12 1996-01-02 Kabushiki Kaisha Toshiba Logic program comparison method for verifying a computer program in relation to a system specification
CA2147536A1 (en) * 1994-06-01 1995-12-02 Gerard Johan Holzmann On-the-fly model checking with partial-order state space reduction

Also Published As

Publication number Publication date
ATE217714T1 (de) 2002-06-15
EP0828215A1 (de) 1998-03-11
EP0828215B1 (de) 2002-05-15
DE59707264D1 (de) 2002-06-20

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