ES2185131T3 - Procedimiento para aislar un ordenador defectuoso en un sistema multiordenador tolerante a los errores. - Google Patents

Procedimiento para aislar un ordenador defectuoso en un sistema multiordenador tolerante a los errores.

Info

Publication number
ES2185131T3
ES2185131T3 ES98440187T ES98440187T ES2185131T3 ES 2185131 T3 ES2185131 T3 ES 2185131T3 ES 98440187 T ES98440187 T ES 98440187T ES 98440187 T ES98440187 T ES 98440187T ES 2185131 T3 ES2185131 T3 ES 2185131T3
Authority
ES
Spain
Prior art keywords
computer
defective
command
procedure
computers
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
ES98440187T
Other languages
English (en)
Inventor
Kurt Preisinger
Andre Fitzke
Heinz Dr Kantz
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Alcatel Lucent SAS
Nokia Inc
Original Assignee
Alcatel SA
Nokia Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Alcatel SA, Nokia Inc filed Critical Alcatel SA
Application granted granted Critical
Publication of ES2185131T3 publication Critical patent/ES2185131T3/es
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/16—Error detection or correction of the data by redundancy in hardware
    • G06F11/18—Error detection or correction of the data by redundancy in hardware using passive fault-masking of the redundant circuits
    • G06F11/181—Eliminating the failing redundant component
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/0796—Safety measures, i.e. ensuring safe condition in the event of error, e.g. for controlling element
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/16—Error detection or correction of the data by redundancy in hardware
    • G06F11/18—Error detection or correction of the data by redundancy in hardware using passive fault-masking of the redundant circuits
    • G06F11/182—Error detection or correction of the data by redundancy in hardware using passive fault-masking of the redundant circuits based on mutual exchange of the output between redundant processing components

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Quality & Reliability (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Hardware Redundancy (AREA)
  • Multi Processors (AREA)

Abstract

EN UN SISTEMA DE ORDENADORES MULTIPLES, EN PARTICULAR EN UN SISTEMA A BASE DE DOS A TRES ORDENADORES, DEBE SER AISLADO UN ORDENADOR RECONOCIDO COMO DEFECTUOSO CONSIDERANDO EL PRINCIPIO "FAIL-SAFE" DE TAL MODO QUE PUEDAN SEGUIR TRABAJANDO SIN EL ORDENADOR DEFECTUOSO. DE ACUERDO CON LA INVENCION EL ORDENADOR DEFECTUOSO OBTIENE A PARTIR DE LOS ORDENADORES NO DEFECTUOSOS UN COMANDO (102), LLEGANDO COMPLETAMENTE Y AJUSTANDO CON ELLO LA ENTREGA DE DATOS. EN CASO DE QUE AL ORDENADOR DEFECTUOSO NO LE LLEGUE ESTE COMANDO Y SE CEDAN DATOS, NO SE GUIAN ESTOS AL ORDENADOR DEFECTUOSO (104). CON ELLO EL SISTEMA TOMA UNA SITUACION SEGURA, QUE PUEDA HACER EN BASE AL PROCESO DE COMPARACION DE SISTEMA INTERNO QUE UN ORDENADOR SOLO NO TENGA NINGUNA SALIDA ACTIVA. LA SOLUCION DE ACUERDO CON LA INVENCION ES CON ELLO ESPECIALMENTE APROPIADA PARA SISTEMAS DE CONTROL QUE OBEDECEN DE ACUERDO CON EL PRINCIPIO "FAIL SAFE", TAL COMO SE REQUIERE EN LA SEGURIDAD DE VIAS DE PASO EN TRAFICO FERROVIARIO O EN LA SUPERVISIONDE CENTRALES NUCLEARES. EL PROCEDIMIENTO PUEDE SER REALIZADO COMPLETAMENTE COMO SOFTWARE; SIENDO SUPERFLUO EL INTERRUPTOR DE RELE NECESARIO.
ES98440187T 1997-09-12 1998-08-28 Procedimiento para aislar un ordenador defectuoso en un sistema multiordenador tolerante a los errores. Expired - Lifetime ES2185131T3 (es)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
DE19740136A DE19740136A1 (de) 1997-09-12 1997-09-12 Verfahren zur Isolation eines defekten Rechners in einem fehlertoleranten Mehrrechnersystem

Publications (1)

Publication Number Publication Date
ES2185131T3 true ES2185131T3 (es) 2003-04-16

Family

ID=7842147

Family Applications (1)

Application Number Title Priority Date Filing Date
ES98440187T Expired - Lifetime ES2185131T3 (es) 1997-09-12 1998-08-28 Procedimiento para aislar un ordenador defectuoso en un sistema multiordenador tolerante a los errores.

Country Status (4)

Country Link
EP (1) EP0902369B1 (es)
AT (1) ATE230132T1 (es)
DE (2) DE19740136A1 (es)
ES (1) ES2185131T3 (es)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE19831720A1 (de) 1998-07-15 2000-01-20 Alcatel Sa Verfahren zur Ermittlung einer einheitlichen globalen Sicht vom Systemzustand eines verteilten Rechnernetzwerks
EP1148396A1 (de) * 2000-04-22 2001-10-24 Siemens Schweiz AG Überwachung vernetzter Datenverarbeitungsanlagen
DE10055424A1 (de) * 2000-11-09 2002-05-29 Alcatel Sa Verfahren zum Speichern eines Sicherheitsschlüssels und Mehrrechnersystem zur Durchführung des Verfahrens
JP5390532B2 (ja) 2008-11-26 2014-01-15 パナソニック株式会社 監視システム、プログラム実行装置、監視プログラム、記録媒体及び集積回路

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3208573C2 (de) * 1982-03-10 1985-06-27 Standard Elektrik Lorenz Ag, 7000 Stuttgart 2 aus 3-Auswahleinrichtung für ein 3-Rechnersystem
DE3431169A1 (de) * 1984-08-24 1986-03-06 Standard Elektrik Lorenz Ag, 7000 Stuttgart Verfahren zur synchronisation mehrerer parallelarbeitender rechner
DE3787045D1 (de) * 1986-05-14 1993-09-23 Alcatel Austria Ag Fehlertolerantes datenverarbeitungssystem.
ATE110477T1 (de) * 1990-08-14 1994-09-15 Siemens Ag Mehrrechnersystem hoher sicherheit mit drei rechnern.
DE4135640A1 (de) * 1991-10-29 1993-05-06 Industronic Industrie-Electronic Gmbh & Co Kg, 6980 Wertheim, De Dreifach redundante rechner-einrichtung

Also Published As

Publication number Publication date
ATE230132T1 (de) 2003-01-15
DE59806695D1 (de) 2003-01-30
EP0902369A2 (de) 1999-03-17
EP0902369B1 (de) 2002-12-18
DE19740136A1 (de) 1999-03-18
EP0902369A3 (de) 1999-07-28

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