ES2193553T3 - Procedimiento para la produccion de un modulo de chip. - Google Patents

Procedimiento para la produccion de un modulo de chip.

Info

Publication number
ES2193553T3
ES2193553T3 ES98943710T ES98943710T ES2193553T3 ES 2193553 T3 ES2193553 T3 ES 2193553T3 ES 98943710 T ES98943710 T ES 98943710T ES 98943710 T ES98943710 T ES 98943710T ES 2193553 T3 ES2193553 T3 ES 2193553T3
Authority
ES
Spain
Prior art keywords
chip module
procedure
production
chip holder
chip
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
ES98943710T
Other languages
English (en)
Inventor
Frank Puschner
Jurgen Fischer
Erik Heinemann
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Infineon Technologies AG
Original Assignee
Infineon Technologies AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Family has litigation
First worldwide family litigation filed litigation Critical https://patents.darts-ip.com/?family=7837429&utm_source=google_patent&utm_medium=platform_link&utm_campaign=public_patent_search&patent=ES2193553(T3) "Global patent litigation dataset” by Darts-ip is licensed under a Creative Commons Attribution 4.0 International License.
Application filed by Infineon Technologies AG filed Critical Infineon Technologies AG
Application granted granted Critical
Publication of ES2193553T3 publication Critical patent/ES2193553T3/es
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06K—GRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
    • G06K19/00—Record carriers for use with machines and with at least a part designed to carry digital markings
    • G06K19/06—Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
    • G06K19/067—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
    • G06K19/07—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
    • G06K19/077—Constructional details, e.g. mounting of circuits in the carrier
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06K—GRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
    • G06K19/00—Record carriers for use with machines and with at least a part designed to carry digital markings
    • G06K19/06—Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
    • G06K19/067—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
    • G06K19/07—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
    • G06K19/077—Constructional details, e.g. mounting of circuits in the carrier
    • G06K19/07745—Mounting details of integrated circuit chips
    • G06K19/07747—Mounting details of integrated circuit chips at least one of the integrated circuit chips being mounted as a module
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06K—GRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
    • G06K19/00—Record carriers for use with machines and with at least a part designed to carry digital markings
    • G06K19/06—Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
    • G06K19/067—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
    • G06K19/07—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
    • G06K19/077—Constructional details, e.g. mounting of circuits in the carrier
    • G06K19/07745—Mounting details of integrated circuit chips
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/111—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed
    • H10W74/127—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed characterised by arrangements for sealing or adhesion

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Credit Cards Or The Like (AREA)
  • Lead Frames For Integrated Circuits (AREA)
  • Wire Bonding (AREA)
  • Die Bonding (AREA)

Abstract

La invención se refiere a un procedimiento de producción de un módulo de chip, según el cual, después des estampado de un porta-chip (1), la distancia (a) que separa la sección de fijación (6) del porte-chip y las secciones de contacto (4) del porta-chip se reduce, mediante un aplastamiento efectuado al menos en la zona cercana a unas ranuras, a una dimensión que impide el paso de la masa de sellado (5).
ES98943710T 1997-07-30 1998-07-21 Procedimiento para la produccion de un modulo de chip. Expired - Lifetime ES2193553T3 (es)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
DE19732915A DE19732915C1 (de) 1997-07-30 1997-07-30 Verfahren zur Herstellung eines Chipmoduls

Publications (1)

Publication Number Publication Date
ES2193553T3 true ES2193553T3 (es) 2003-11-01

Family

ID=7837429

Family Applications (1)

Application Number Title Priority Date Filing Date
ES98943710T Expired - Lifetime ES2193553T3 (es) 1997-07-30 1998-07-21 Procedimiento para la produccion de un modulo de chip.

Country Status (12)

Country Link
US (1) US6472250B1 (es)
EP (1) EP0998724B1 (es)
JP (1) JP3490680B2 (es)
KR (1) KR100366678B1 (es)
CN (1) CN1207688C (es)
AT (1) ATE233418T1 (es)
BR (1) BR9811564A (es)
DE (2) DE19732915C1 (es)
ES (1) ES2193553T3 (es)
RU (1) RU2181504C2 (es)
UA (1) UA48314C2 (es)
WO (1) WO1999006947A1 (es)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8088386B2 (en) * 1998-03-20 2012-01-03 Genentech, Inc. Treatment of complement-associated disorders
JP3876953B2 (ja) * 1998-03-27 2007-02-07 セイコーエプソン株式会社 半導体装置及びその製造方法、回路基板並びに電子機器
JP3664045B2 (ja) * 2000-06-01 2005-06-22 セイコーエプソン株式会社 半導体装置の製造方法
DE10202727A1 (de) * 2002-01-24 2003-08-21 Infineon Technologies Ag Trägersubstrat für ein Chipmodul, Chipmodul und Chipkarte
US20040010965A1 (en) * 2002-07-09 2004-01-22 Clariant Gmbh Oxidation-stabilized lubricant additives for highly desulfurized fuel oils
US7400049B2 (en) * 2006-02-16 2008-07-15 Stats Chippac Ltd. Integrated circuit package system with heat sink
WO2010019067A1 (ru) * 2008-08-08 2010-02-18 Dolgih Vyacheslav Olegovich Персональный носитель данных
ES2439508T3 (es) * 2011-08-25 2014-01-23 Textilma Ag Módulo de chip RFID
CN104600172A (zh) * 2014-09-10 2015-05-06 广东长盈精密技术有限公司 倒装芯片型led支架及其制造方法

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
SU1583995A1 (ru) * 1987-06-30 1990-08-07 Предприятие П/Я Р-6429 Интегральна микросхема
US5122860A (en) * 1987-08-26 1992-06-16 Matsushita Electric Industrial Co., Ltd. Integrated circuit device and manufacturing method thereof
JPH01106456A (ja) 1987-10-19 1989-04-24 Matsushita Electric Ind Co Ltd 半導体集積回路装置
FR2636453B1 (fr) * 1988-09-14 1992-01-17 Sgs Thomson Microelectronics Procede d'encapsulation de circuits-integres notamment pour cartes a puces
FR2659157B2 (fr) 1989-05-26 1994-09-30 Lemaire Gerard Procede de fabrication d'une carte dite carte a puce, et carte obtenue par ce procede.
US5028741A (en) * 1990-05-24 1991-07-02 Motorola, Inc. High frequency, power semiconductor device
KR940010548B1 (ko) * 1991-12-05 1994-10-24 삼성전자 주식회사 반도체 리드 프레임
RU2039397C1 (ru) * 1992-06-08 1995-07-09 Людмила Георгиевна Царева Способ изготовления микросборки
DE4336501A1 (de) * 1993-10-26 1995-04-27 Giesecke & Devrient Gmbh Verfahren zur Herstellung von Ausweiskarten mit elektronischen Modulen
DE4443767A1 (de) * 1994-12-08 1996-06-13 Giesecke & Devrient Gmbh Elektronisches Modul und Datenträger mit elektrischem Modul
DE19513797A1 (de) * 1995-04-11 1996-10-24 Siemens Ag Verfahren zum Herstellen eines Trägerelementes und Vorrichtung zur Durchführung des Verfahrens

Also Published As

Publication number Publication date
RU2181504C2 (ru) 2002-04-20
DE19732915C1 (de) 1998-12-10
UA48314C2 (uk) 2002-08-15
DE59807325D1 (de) 2003-04-03
WO1999006947A1 (de) 1999-02-11
EP0998724A1 (de) 2000-05-10
KR20010022252A (ko) 2001-03-15
JP2001512289A (ja) 2001-08-21
JP3490680B2 (ja) 2004-01-26
CN1207688C (zh) 2005-06-22
EP0998724B1 (de) 2003-02-26
BR9811564A (pt) 2000-09-12
CN1265759A (zh) 2000-09-06
ATE233418T1 (de) 2003-03-15
US6472250B1 (en) 2002-10-29
KR100366678B1 (ko) 2003-01-09

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