ES2644268T3 - Proceso para rellenar surcos de contacto en microelectrónica - Google Patents

Proceso para rellenar surcos de contacto en microelectrónica Download PDF

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Publication number
ES2644268T3
ES2644268T3 ES12703929.5T ES12703929T ES2644268T3 ES 2644268 T3 ES2644268 T3 ES 2644268T3 ES 12703929 T ES12703929 T ES 12703929T ES 2644268 T3 ES2644268 T3 ES 2644268T3
Authority
ES
Spain
Prior art keywords
microelectronics
contact grooves
filling contact
filling
grooves
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
ES12703929.5T
Other languages
English (en)
Inventor
Thomas B. Richardson
Joseph A. Abys
Wenbo Shao
Chen Wang
Jr. Vincent Paneccasio
Cai Wang
Xuan Lin
Theodore Antonellis
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
MacDermid Enthone Inc
Original Assignee
MacDermid Enthone Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by MacDermid Enthone Inc filed Critical MacDermid Enthone Inc
Application granted granted Critical
Publication of ES2644268T3 publication Critical patent/ES2644268T3/es
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10PGENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/40Formation of materials, e.g. in the shape of layers or pillars of conductive or resistive materials
    • H10P14/46Formation of materials, e.g. in the shape of layers or pillars of conductive or resistive materials using a liquid
    • H10P14/47Electrolytic deposition, i.e. electroplating; Electroless plating
    • CCHEMISTRY; METALLURGY
    • C25ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25DPROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D3/00Electroplating: Baths therefor
    • C25D3/02Electroplating: Baths therefor from solutions
    • C25D3/38Electroplating: Baths therefor from solutions of copper
    • CCHEMISTRY; METALLURGY
    • C25ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25DPROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D5/00Electroplating characterised by the process; Pretreatment or after-treatment of workpieces
    • C25D5/02Electroplating of selected surface areas
    • CCHEMISTRY; METALLURGY
    • C25ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25DPROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D5/00Electroplating characterised by the process; Pretreatment or after-treatment of workpieces
    • C25D5/18Electroplating using modulated, pulsed or reversing current
    • CCHEMISTRY; METALLURGY
    • C25ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25DPROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D5/00Electroplating characterised by the process; Pretreatment or after-treatment of workpieces
    • C25D5/60Electroplating characterised by the structure or texture of the layers
    • C25D5/605Surface topography of the layers, e.g. rough, dendritic or nodular layers
    • C25D5/611Smooth layers
    • CCHEMISTRY; METALLURGY
    • C25ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25DPROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D7/00Electroplating characterised by the article coated
    • C25D7/12Semiconductors
    • C25D7/123Semiconductors first coated with a seed layer or a conductive layer
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00Interconnections in chips, wafers or substrates
    • H10W20/01Manufacture or treatment
    • H10W20/021Manufacture or treatment of interconnections within wafers or substrates
    • H10W20/023Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00Interconnections in chips, wafers or substrates
    • H10W20/01Manufacture or treatment
    • H10W20/021Manufacture or treatment of interconnections within wafers or substrates
    • H10W20/023Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias
    • H10W20/0245Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias comprising use of blind vias during the manufacture
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00Interconnections in chips, wafers or substrates
    • H10W20/01Manufacture or treatment
    • H10W20/021Manufacture or treatment of interconnections within wafers or substrates
    • H10W20/023Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias
    • H10W20/0261Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias characterised by the filling method or the material of the conductive fill
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00Interconnections in chips, wafers or substrates
    • H10W20/01Manufacture or treatment
    • H10W20/031Manufacture or treatment of conductive parts of the interconnections
    • H10W20/032Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers
    • H10W20/042Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers the barrier, adhesion or liner layers being seed or nucleation layers
    • H10W20/043Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers the barrier, adhesion or liner layers being seed or nucleation layers for electroplating
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00Interconnections in chips, wafers or substrates
    • H10W20/01Manufacture or treatment
    • H10W20/031Manufacture or treatment of conductive parts of the interconnections
    • H10W20/056Manufacture or treatment of conductive parts of the interconnections by filling conductive material into holes, grooves or trenches
    • H10W20/057Manufacture or treatment of conductive parts of the interconnections by filling conductive material into holes, grooves or trenches by selectively depositing, e.g. by using selective CVD or plating

Landscapes

  • Chemical & Material Sciences (AREA)
  • Organic Chemistry (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Electrochemistry (AREA)
  • Materials Engineering (AREA)
  • Metallurgy (AREA)
  • Engineering & Computer Science (AREA)
  • Electroplating Methods And Accessories (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Electroplating And Plating Baths Therefor (AREA)
  • Inks, Pencil-Leads, Or Crayons (AREA)
  • Coating Apparatus (AREA)

Description

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Claims (1)

  1. imagen1
    imagen2
ES12703929.5T 2011-01-26 2012-01-26 Proceso para rellenar surcos de contacto en microelectrónica Active ES2644268T3 (es)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US201161436569P 2011-01-26 2011-01-26
US201161436569P 2011-01-26
PCT/US2012/022758 WO2012103357A1 (en) 2011-01-26 2012-01-26 Process for filling vias in the microelectronics

Publications (1)

Publication Number Publication Date
ES2644268T3 true ES2644268T3 (es) 2017-11-28

Family

ID=45592815

Family Applications (1)

Application Number Title Priority Date Filing Date
ES12703929.5T Active ES2644268T3 (es) 2011-01-26 2012-01-26 Proceso para rellenar surcos de contacto en microelectrónica

Country Status (7)

Country Link
US (2) US10541140B2 (es)
EP (1) EP2668317B1 (es)
JP (1) JP5981455B2 (es)
KR (1) KR101817823B1 (es)
CN (1) CN103492617B (es)
ES (1) ES2644268T3 (es)
WO (1) WO2012103357A1 (es)

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JP5981455B2 (ja) 2011-01-26 2016-08-31 エンソン インコーポレイテッド マイクロ電子工業におけるビアホール充填方法
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EP2865787A1 (en) 2013-10-22 2015-04-29 ATOTECH Deutschland GmbH Copper electroplating method
US10147510B1 (en) * 2013-11-15 2018-12-04 National Technology & Engineering Solutions Of Sandia, Llc Electroplated AU for conformal coating of high aspect ratio silicon structures
US20150233008A1 (en) * 2014-02-13 2015-08-20 Skyworks Solutions, Inc. Apparatus and methods related to copper plating of wafers
US9809891B2 (en) 2014-06-30 2017-11-07 Rohm And Haas Electronic Materials Llc Plating method
WO2017004424A1 (en) * 2015-06-30 2017-01-05 Enthone Inc. Cobalt filling of interconnects in microelectronics
CN105441994B (zh) * 2015-12-30 2017-09-19 上海新阳半导体材料股份有限公司 一种能用于提高凸点共面性的电镀液组合物
US10519557B2 (en) 2016-02-12 2019-12-31 Macdermid Enthone Inc. Leveler compositions for use in copper deposition in manufacture of microelectronics
JP6573575B2 (ja) * 2016-05-02 2019-09-11 東京エレクトロン株式会社 凹部の埋め込み方法
US9793156B1 (en) * 2016-09-12 2017-10-17 International Business Machines Corporation Self-aligned low resistance metallic interconnect structures
CN109996785B (zh) * 2016-09-22 2021-12-28 麦克德米德乐思公司 集成电路的晶圆级封装中的铜沉积
EP3360988B1 (en) * 2017-02-09 2019-06-26 ATOTECH Deutschland GmbH Pyridinium compounds, a synthesis method therefor, metal or metal alloy plating baths containing said pyridinium compounds and a method for use of said metal or metal alloy plating baths
US10103056B2 (en) * 2017-03-08 2018-10-16 Lam Research Corporation Methods for wet metal seed deposition for bottom up gapfill of features
US10458032B2 (en) * 2017-06-15 2019-10-29 Rohm And Haas Electronic Materials Llc Environmentally friendly nickel electroplating compositions and methods
US10508348B2 (en) * 2017-06-15 2019-12-17 Rohm And Haas Electronic Materials Llc Environmentally friendly nickel electroplating compositions and methods
JP6904194B2 (ja) * 2017-09-22 2021-07-14 住友金属鉱山株式会社 配線基板用積層体及びその製造方法
JP6904195B2 (ja) * 2017-09-22 2021-07-14 住友金属鉱山株式会社 フレキシブル配線基板及びその製造方法
CN109244053B (zh) * 2018-09-17 2020-04-14 上海交通大学 一种提高tsv热机械可靠性的复合结构及其制造方法
US11823896B2 (en) * 2019-02-22 2023-11-21 Taiwan Semiconductor Manufacturing Co., Ltd. Conductive structure formed by cyclic chemical vapor deposition
KR102748951B1 (ko) * 2019-06-25 2025-01-02 삼성전기주식회사 인쇄회로기판 도금 방법 및 인쇄회로기판
CN114514340B (zh) 2019-07-26 2025-03-21 朗姆研究公司 先进封装应用的差别对比镀覆
US11581264B2 (en) * 2019-08-21 2023-02-14 Micron Technology, Inc. Electronic devices comprising overlay marks, memory devices comprising overlay marks, and related methods
KR102818620B1 (ko) 2019-12-20 2025-06-10 삼성전자주식회사 물질막 형성 방법과, 집적회로 소자 및 그 제조 방법
US12305307B2 (en) * 2020-01-10 2025-05-20 Lam Research Corporation TSV process window and fill performance enhancement by long pulsing and ramping
US20250149380A1 (en) * 2023-11-02 2025-05-08 Taiwan Semiconductor Manufacturing Co., Ltd. Interconnect structure and method of forming same
CN119287460B (zh) * 2024-12-10 2025-03-14 深圳市联合蓝海应用材料科技股份有限公司 一种电镀铜整平剂及制备方法、电镀液及电镀方法与产品

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JP5981455B2 (ja) 2011-01-26 2016-08-31 エンソン インコーポレイテッド マイクロ電子工業におけるビアホール充填方法

Also Published As

Publication number Publication date
KR101817823B1 (ko) 2018-02-21
EP2668317A1 (en) 2013-12-04
US20160254156A1 (en) 2016-09-01
US10103029B2 (en) 2018-10-16
EP2668317B1 (en) 2017-08-23
US20140120722A1 (en) 2014-05-01
CN103492617A (zh) 2014-01-01
JP2014508859A (ja) 2014-04-10
CN103492617B (zh) 2017-04-19
KR20140008517A (ko) 2014-01-21
US10541140B2 (en) 2020-01-21
WO2012103357A1 (en) 2012-08-02
JP5981455B2 (ja) 2016-08-31

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