ES335355A1 - IMPROVEMENTS IN THE CONSTRUCTION OF ELECTRONIC ARITHMETIC DIVIDERS. - Google Patents

Abstract

Perfections in the construction of electronic arithmetic dividers of the type that effects the division of a number B (dividend) between a number D (divisor) by means of a succession of subtractions and additions, all having a second term D and whose first term is the subtraction B-D, consisting of an electronic assembly comprising a memory register for the divider D, this register being constituted by a series of memories, an accumulator register for the dividend B, this register being constituted by a series of memories, a adding system connected to the memory register of the divider D and to the accumulator register containing the dividend B and a register of quotient memories, characterized in that said arithmetic divisor comprises, between the memory register of the divider D and the adding system a selector system susceptible to receive a signal due to a division order or from the record of co memories and the adding system is capable of sending a retention signal that is communicated to its input at the beginning of the next cycle, and that is recorded in the memory of quotients memory, while the memory of the accumulator record of the highest order it is capable of sending a signal to the adder, the assembly being such that, on the one hand, when the subtraction imposed on the apparatus is arithmetically possible, that is to say, BD> D, the apparatus, once the addition B + D has been made ( being D the complementary subtrahend of D) and before the displacement towards the cell of greater weight of the register of memories of quotients, it works in such a way that the adder sends a signal that allows to obtain B - D from B + D and that registers 1 in the memory of ratios of quotients, sending the latter, after said displacement, a signal to the selector system, whence it turns out that it reverses the signals emitted by the memory. of the divisor in the course of the following subtraction imposed on the apparatus and that, on the other hand, when the subtraction imposed on the apparatus is arithmetically impossible (ie such that B-B <0), the apparatus, once the addition B + D works in such a way that the absence of a signal in the register of quotient memories has the effect that it registers a null quotient and that the selector system does not reverse the signals emitted by the memories of the splitter in the course of the aforementioned next arithmetic operation. (Machine-translation by Google Translate, not legally binding)