ES345367A1 - Decoders for encoded digital signals - Google Patents

Abstract

In a decoder, e.g. for a PCM system, a logic circuit 1 receives a digital coded signal in serial form and controls a digital-to-analogue converter 2 to produce analogue signals of a single polarity, which are applied in true and inverted form to switches 5 and 6 having a common output point 11 connected, via a capacitor 12, to a high-impedance output amplifier 14, the capacitor being connected to earth by a third switch. The capacitor 12 and switch 15 compensate for the " offset " voltages of the switches 5 and 6. These are electronic switches and the offset voltage may be regarded as a battery in series with an ideal switch. When the capacitor is earthed on the remote side it is charged to the value of the offset voltage but in a direction opposite to the offset voltage. When converter 3 produces its output signal, this and the offset voltage are applied to the capacitor. The charge on the capacitor cancels the offset voltage, leaving the correct analogue equivalent of the digital input. The sign of the sample value is given by the first digit. This digit appears on the first output terminal when the coded signal is read into the control logic 1 and is used to select one of the switches. The switch 15 is then briefly closed so that the offset voltage of the selected switch is applied to the capacitor 12. A timing signal controls switch 15. The characteristic of the converter is non-linear to improve the quality of transmitted speech signals.