ES476008A1 - IMPROVEMENTS IN MULTI-STAGE LOGIC CIRCUITS. - Google Patents
IMPROVEMENTS IN MULTI-STAGE LOGIC CIRCUITS.Info
- Publication number
- ES476008A1 ES476008A1 ES476008A ES476008A ES476008A1 ES 476008 A1 ES476008 A1 ES 476008A1 ES 476008 A ES476008 A ES 476008A ES 476008 A ES476008 A ES 476008A ES 476008 A1 ES476008 A1 ES 476008A1
- Authority
- ES
- Spain
- Prior art keywords
- stages
- logic circuits
- stage logic
- successive
- successive stages
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
- H03K19/094—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors
- H03K19/096—Synchronous circuits, i.e. using clock signals
- H03K19/0963—Synchronous circuits, i.e. using clock signals using transistors of complementary type
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/01—Modifications for accelerating switching
- H03K19/017—Modifications for accelerating switching in field-effect transistor circuits
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Computing Systems (AREA)
- General Engineering & Computer Science (AREA)
- Mathematical Physics (AREA)
- Power Engineering (AREA)
- Logic Circuits (AREA)
- Control Of El Displays (AREA)
- Manipulation Of Pulses (AREA)
Abstract
Individual stages (S1, S2, S3) of a multistage logic circuit arrangement are accessed at improved speeds by activating all of the stages simultaneously by the same clock pulse (16). To prevent premature, non-sequential operation of the successive stages of the circuit, means (20, 81) are provided for inhibiting or delaying operation of the successive stages until the preceding stages have performed their logic function.
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US86033977A | 1977-12-14 | 1977-12-14 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| ES476008A1 true ES476008A1 (en) | 1979-05-01 |
Family
ID=25332993
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| ES476008A Expired ES476008A1 (en) | 1977-12-14 | 1978-12-14 | IMPROVEMENTS IN MULTI-STAGE LOGIC CIRCUITS. |
Country Status (6)
| Country | Link |
|---|---|
| JP (1) | JPS5489558A (en) |
| DE (1) | DE2853517A1 (en) |
| ES (1) | ES476008A1 (en) |
| GB (1) | GB2013438A (en) |
| IT (1) | IT1101554B (en) |
| NL (1) | NL7812138A (en) |
Families Citing this family (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5632831A (en) * | 1979-08-24 | 1981-04-02 | Mitsubishi Electric Corp | Clock driving type logic circuit |
| US4636661A (en) * | 1984-12-21 | 1987-01-13 | Signetics Corporation | Ratioless FET programmable logic array |
| US4692637A (en) * | 1985-07-08 | 1987-09-08 | At&T Bell Laboratories | CMOS logic circuit with single clock pulse |
| US5065048A (en) * | 1988-09-19 | 1991-11-12 | Hitachi, Ltd. | Semiconductor logic circuit with noise suppression circuit |
| US6717438B2 (en) * | 2002-08-30 | 2004-04-06 | Sun Microsystems, Inc. | Clocked half-rail differential logic with single-rail logic |
| JP5322977B2 (en) * | 2010-03-04 | 2013-10-23 | 株式会社エヌ・ティ・ティ・データ | Power consumption confusion type logic circuit and information storage medium |
-
1978
- 1978-12-12 DE DE19782853517 patent/DE2853517A1/en not_active Withdrawn
- 1978-12-13 IT IT30789/78A patent/IT1101554B/en active
- 1978-12-13 NL NL7812138A patent/NL7812138A/en not_active Application Discontinuation
- 1978-12-14 ES ES476008A patent/ES476008A1/en not_active Expired
- 1978-12-14 JP JP15377678A patent/JPS5489558A/en active Pending
- 1978-12-14 GB GB7848568A patent/GB2013438A/en not_active Withdrawn
Also Published As
| Publication number | Publication date |
|---|---|
| IT1101554B (en) | 1985-10-07 |
| DE2853517A1 (en) | 1979-06-21 |
| JPS5489558A (en) | 1979-07-16 |
| NL7812138A (en) | 1979-06-18 |
| GB2013438A (en) | 1979-08-08 |
| IT7830789A0 (en) | 1978-12-13 |
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