ES523747A0 - Sistema de proceso de control de acceso en un sistema de ordenador. - Google Patents

Sistema de proceso de control de acceso en un sistema de ordenador.

Info

Publication number
ES523747A0
ES523747A0 ES523747A ES523747A ES523747A0 ES 523747 A0 ES523747 A0 ES 523747A0 ES 523747 A ES523747 A ES 523747A ES 523747 A ES523747 A ES 523747A ES 523747 A0 ES523747 A0 ES 523747A0
Authority
ES
Spain
Prior art keywords
access control
control process
computer system
process system
computer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
ES523747A
Other languages
English (en)
Other versions
ES8502558A1 (es
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from JP57112862A external-priority patent/JPS593774A/ja
Priority claimed from JP57154950A external-priority patent/JPS5945570A/ja
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Publication of ES8502558A1 publication Critical patent/ES8502558A1/es
Publication of ES523747A0 publication Critical patent/ES523747A0/es
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/18—Handling requests for interconnection or transfer for access to memory bus based on priority control

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Multi Processors (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
ES523747A 1982-06-30 1983-06-30 Sistema de proceso de control de acceso en un sistema de ordenador. Granted ES523747A0 (es)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP57112862A JPS593774A (ja) 1982-06-30 1982-06-30 アクセス処理方式
JP57154950A JPS5945570A (ja) 1982-09-06 1982-09-06 アクセス処理方式

Publications (2)

Publication Number Publication Date
ES8502558A1 ES8502558A1 (es) 1985-01-01
ES523747A0 true ES523747A0 (es) 1985-01-01

Family

ID=26451932

Family Applications (1)

Application Number Title Priority Date Filing Date
ES523747A Granted ES523747A0 (es) 1982-06-30 1983-06-30 Sistema de proceso de control de acceso en un sistema de ordenador.

Country Status (7)

Country Link
EP (1) EP0098170B1 (es)
KR (1) KR870000117B1 (es)
AU (1) AU545700B2 (es)
BR (1) BR8303525A (es)
CA (1) CA1199122A (es)
DE (1) DE3380458D1 (es)
ES (1) ES523747A0 (es)

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR1541240A (fr) * 1966-11-10 Ibm Accès à chevauchement et à intercalation pour mémoires à plusieurs vitesses
US3705388A (en) * 1969-08-12 1972-12-05 Kogyo Gijutsuin Memory control system which enables access requests during block transfer
DE2048119C3 (de) * 1970-09-30 1978-09-07 Siemens Ag, 1000 Berlin U. 8000 Muenchen Anordnung und Verfahren zur Steuerung der Datenübertragung zwischen externen Geräten und einer Datenverarbeitungsanlage
US3964054A (en) * 1975-06-23 1976-06-15 International Business Machines Corporation Hierarchy response priority adjustment mechanism
US4345309A (en) * 1980-01-28 1982-08-17 Digital Equipment Corporation Relating to cached multiprocessor system with pipeline timing

Also Published As

Publication number Publication date
AU1640783A (en) 1984-01-05
ES8502558A1 (es) 1985-01-01
CA1199122A (en) 1986-01-07
KR870000117B1 (ko) 1987-02-11
EP0098170B1 (en) 1989-08-23
EP0098170A2 (en) 1984-01-11
BR8303525A (pt) 1984-02-07
DE3380458D1 (en) 1989-09-28
AU545700B2 (en) 1985-07-25
EP0098170A3 (en) 1985-08-07
KR840005232A (ko) 1984-11-05

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Legal Events

Date Code Title Description
FD1A Patent lapsed

Effective date: 19971001