ES540478A0 - Perfeccionamientos en dispositivos de circuitos integrados - Google Patents

Perfeccionamientos en dispositivos de circuitos integrados

Info

Publication number
ES540478A0
ES540478A0 ES540478A ES540478A ES540478A0 ES 540478 A0 ES540478 A0 ES 540478A0 ES 540478 A ES540478 A ES 540478A ES 540478 A ES540478 A ES 540478A ES 540478 A0 ES540478 A0 ES 540478A0
Authority
ES
Spain
Prior art keywords
integrated circuit
circuit devices
devices
integrated
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
ES540478A
Other languages
English (en)
Other versions
ES8700500A1 (es
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
AT&T Inc
Original Assignee
American Telephone and Telegraph Co Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US06/581,336 external-priority patent/USH208H/en
Priority claimed from US06/581,259 external-priority patent/US4613891A/en
Priority claimed from US06/582,079 external-priority patent/US4670770A/en
Application filed by American Telephone and Telegraph Co Inc filed Critical American Telephone and Telegraph Co Inc
Publication of ES8700500A1 publication Critical patent/ES8700500A1/es
Publication of ES540478A0 publication Critical patent/ES540478A0/es
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/495—Capacitive arrangements or effects of, or between wiring layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/117—Shapes of semiconductor bodies
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W44/00—Electrical arrangements for controlling or matching impedance
    • H10W44/601—Capacitive arrangements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/099—Connecting interconnections to insulating or insulated package substrates, interposers or redistribution layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/611—Insulating or insulated package substrates; Interposers; Redistribution layers for connecting multiple chips together
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/63—Vias, e.g. via plugs
    • H10W70/635—Through-vias
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
    • H10W70/69—Insulating materials thereof
    • H10W70/698—Semiconductor materials that are electrically insulating, e.g. undoped silicon
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/073—Connecting or disconnecting of die-attach connectors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
ES540478A 1984-02-17 1985-02-15 Perfeccionamientos en dispositivos de circuitos integrados Expired ES8700500A1 (es)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US58126084A 1984-02-17 1984-02-17
US06/581,336 USH208H (en) 1984-02-17 1984-02-17 Packaging microminiature devices
US06/581,259 US4613891A (en) 1984-02-17 1984-02-17 Packaging microminiature devices
US06/582,079 US4670770A (en) 1984-02-21 1984-02-21 Integrated circuit chip-and-substrate assembly

Publications (2)

Publication Number Publication Date
ES8700500A1 ES8700500A1 (es) 1986-11-16
ES540478A0 true ES540478A0 (es) 1986-11-16

Family

ID=27504949

Family Applications (1)

Application Number Title Priority Date Filing Date
ES540478A Expired ES8700500A1 (es) 1984-02-17 1985-02-15 Perfeccionamientos en dispositivos de circuitos integrados

Country Status (4)

Country Link
EP (2) EP0172889A1 (es)
DE (1) DE3572421D1 (es)
ES (1) ES8700500A1 (es)
WO (1) WO1985003806A1 (es)

Families Citing this family (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6281745A (ja) * 1985-10-05 1987-04-15 Fujitsu Ltd ウエハ−規模のｌｓｉ半導体装置とその製造方法
DE3718684A1 (de) * 1987-06-04 1988-12-22 Licentia Gmbh Halbleiterkoerper
FR2618255A1 (fr) * 1987-07-14 1989-01-20 Gen Electric Bloc de conditionnement pour le montage et l'interconnexion de puces semiconductrices.
FR2634322A1 (fr) * 1988-07-13 1990-01-19 Thomson Csf Module semi-conducteur actif hybride obtenu par reconfiguration physique de pastilles, interconnectees par films minces, et procede de fabrication correspondant
DE68910327T2 (de) * 1988-07-22 1994-05-19 Nippon Denso Co Halbleiteranordnung.
US4989063A (en) * 1988-12-09 1991-01-29 The United States Of America As Represented By The Secretary Of The Air Force Hybrid wafer scale microcircuit integration
US5008213A (en) * 1988-12-09 1991-04-16 The United States Of America As Represented By The Secretary Of The Air Force Hybrid wafer scale microcircuit integration
DE68916784T2 (de) * 1989-04-20 1995-01-05 Ibm Integrierte Schaltungspackung.
US5032896A (en) * 1989-08-31 1991-07-16 Hughes Aircraft Company 3-D integrated circuit assembly employing discrete chips
DE59003592D1 (de) * 1989-09-29 1994-01-05 Siemens Ag Verfahren zur Herstellung eines Körpers aus Silizium.
US6864570B2 (en) 1993-12-17 2005-03-08 The Regents Of The University Of California Method and apparatus for fabricating self-assembling microstructures
JP3701542B2 (ja) * 2000-05-10 2005-09-28 シャープ株式会社 半導体装置およびその製造方法
FR2917234B1 (fr) * 2007-06-07 2009-11-06 Commissariat Energie Atomique Dispositif multi composants integres dans une matrice semi-conductrice.
FR2934082B1 (fr) 2008-07-21 2011-05-27 Commissariat Energie Atomique Dispositif multi composants integres dans une matrice
FR2947948B1 (fr) 2009-07-09 2012-03-09 Commissariat Energie Atomique Plaquette poignee presentant des fenetres de visualisation

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3918148A (en) * 1974-04-15 1975-11-11 Ibm Integrated circuit chip carrier and method for forming the same
GB2047466B (en) * 1979-02-24 1983-03-30 Int Computers Ltd Multi-level connection networks

Also Published As

Publication number Publication date
EP0172889A1 (en) 1986-03-05
EP0154431B1 (en) 1989-08-16
WO1985003806A1 (en) 1985-08-29
ES8700500A1 (es) 1986-11-16
EP0154431A1 (en) 1985-09-11
DE3572421D1 (en) 1989-09-21

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Legal Events

Date Code Title Description
FD1A Patent lapsed

Effective date: 19970612