ES544856A0 - Una configuracion de un circuito para elcontrol de la trans-ferencia bidireccional de datos entre un procesador y las lineas de transmision conectadas a las unidades de entrada- salida - Google Patents

Una configuracion de un circuito para elcontrol de la trans-ferencia bidireccional de datos entre un procesador y las lineas de transmision conectadas a las unidades de entrada- salida

Info

Publication number
ES544856A0
ES544856A0 ES544856A ES544856A ES544856A0 ES 544856 A0 ES544856 A0 ES 544856A0 ES 544856 A ES544856 A ES 544856A ES 544856 A ES544856 A ES 544856A ES 544856 A0 ES544856 A0 ES 544856A0
Authority
ES
Spain
Prior art keywords
transmission lines
input
output units
processor
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
ES544856A
Other languages
English (en)
Other versions
ES8704016A1 (es
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nokia Spain SA
Original Assignee
Alcatel Espana SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Alcatel Espana SA filed Critical Alcatel Espana SA
Publication of ES8704016A1 publication Critical patent/ES8704016A1/es
Publication of ES544856A0 publication Critical patent/ES544856A0/es
Expired legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/24—Handling requests for interconnection or transfer for access to input/output bus using interrupt

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Communication Control (AREA)
  • Bus Control (AREA)
  • Multi Processors (AREA)
  • Information Transfer Systems (AREA)
  • Bidirectional Digital Transmission (AREA)
  • Computer And Data Communications (AREA)
  • Image Processing (AREA)
  • Logic Circuits (AREA)
ES544856A 1984-07-04 1985-07-04 Una configuracion de un circuito para elcontrol de la trans-ferencia bidireccional de datos entre un procesador y las lineas de transmision conectadas a las unidades de entrada- salida Expired ES8704016A1 (es)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
DE19843424587 DE3424587A1 (de) 1984-07-04 1984-07-04 Schaltungsanordnung zur steuerung der bidirektionalen datenuebertragung zwischen einer rechnereinheit und ueber ein-/ausgabeeinheiten angeschlossenen uebertragungsleitungen

Publications (2)

Publication Number Publication Date
ES8704016A1 ES8704016A1 (es) 1987-02-01
ES544856A0 true ES544856A0 (es) 1987-02-01

Family

ID=6239816

Family Applications (1)

Application Number Title Priority Date Filing Date
ES544856A Expired ES8704016A1 (es) 1984-07-04 1985-07-04 Una configuracion de un circuito para elcontrol de la trans-ferencia bidireccional de datos entre un procesador y las lineas de transmision conectadas a las unidades de entrada- salida

Country Status (5)

Country Link
EP (1) EP0170876B1 (es)
AT (1) ATE69320T1 (es)
BE (1) BE902811A (es)
DE (2) DE3424587A1 (es)
ES (1) ES8704016A1 (es)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2203616B (en) * 1987-04-01 1991-10-02 Digital Equipment Int Improvements in or relating to data communication systems
DE3727072A1 (de) * 1987-08-14 1989-02-23 Bernd Ihlow Zusatzeinrichtung fuer anlagen mit datenerfassung sowie -ausgabe
US5299315A (en) * 1992-09-17 1994-03-29 International Business Machines Corp. Personal computer with programmable threshold FIFO registers for data transfer
DE4336353C2 (de) * 1992-12-02 1999-04-22 Siemens Ag Mikroprozessor mit einer integrierten Bussteuereinheit
DE4417286A1 (de) * 1994-05-13 1995-11-23 Deutsche Bundespost Telekom Verfahren und Schaltungsanordnung zum Auslesen von Daten aus Pufferspeichern in ATM-Einrichtungen
DE10017362B4 (de) * 2000-04-07 2004-02-12 Infineon Technologies Ag Einrichtung und Verfahren zur Datenübergabe zwischen zwei Recheneinheiten

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4228496A (en) * 1976-09-07 1980-10-14 Tandem Computers Incorporated Multiprocessor system
FR2440058A1 (fr) * 1978-10-27 1980-05-23 Materiel Telephonique Systeme de memoire tampon pour unite d'echange entre deux unites fonctionnelles et procede de mise en oeuvre
US4258418A (en) * 1978-12-28 1981-03-24 International Business Machines Corporation Variable capacity data buffer system

Also Published As

Publication number Publication date
BE902811A (fr) 1986-01-06
DE3424587A1 (de) 1986-01-09
EP0170876B1 (de) 1991-11-06
ES8704016A1 (es) 1987-02-01
ATE69320T1 (de) 1991-11-15
EP0170876A3 (en) 1988-08-10
DE3584592D1 (de) 1991-12-12
EP0170876A2 (de) 1986-02-12

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Legal Events

Date Code Title Description
FD1A Patent lapsed

Effective date: 19971001