ES8401697A1 - Perfeccionamientos en una matriz de conmutacion por division de tiempo. - Google Patents
Perfeccionamientos en una matriz de conmutacion por division de tiempo.Info
- Publication number
- ES8401697A1 ES8401697A1 ES515618A ES515618A ES8401697A1 ES 8401697 A1 ES8401697 A1 ES 8401697A1 ES 515618 A ES515618 A ES 515618A ES 515618 A ES515618 A ES 515618A ES 8401697 A1 ES8401697 A1 ES 8401697A1
- Authority
- ES
- Spain
- Prior art keywords
- signals
- data
- lines
- parallel
- control
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04Q—SELECTING
- H04Q11/00—Selecting arrangements for multiplex systems
- H04Q11/04—Selecting arrangements for multiplex systems for time-division multiplexing
Landscapes
- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Time-Division Multiplex Systems (AREA)
- Use Of Switch Circuits For Exchanges And Methods Of Control Of Multiplex Exchanges (AREA)
Abstract
PERFECCIONAMIENTOS EN UNA MATRIZ QUE CONMUTA UN GRUPO DE LINEAS DE ENTRADA DE PCM EN UN GRUPO DE LINEAS DE SALIDA.COMPRENDE LOS SIGUIENTES ELEMENTOS: A) MEDIOS CONVERTIDORES DE SERIE A PARALELO (101 A, 101 B) PARA RECIBIR SEÑALES MULTIPLEXADAS POR DIVISION DE TIEMPO PROCEDENTES DE UNA PLURALIDAD DE LINEAS DE ENTRADA Y PARA CONVERTIR LAS SEÑALES EN SECUENCIA EN FORMA PARALELA; MEDIOS DE MEMORIA DE DATOS (102 A, 102 B) PARA RECIBIR LAS SEÑALES DE FORMA PARALELA Y ALMACENARLAS; C) MEDIOS PARA RECIBIR SEÑALES DE CONTROL DE UNA PLURALIDAD DE LINEAS DE CONTROL, COMPUESTAS DE BITIOSDE DIRECCIONES Y DE DATOS; D) UNA MEMORIA DE CONEXION (107 A, 107 B), PARA ALMACENAR LOS BITIOS DE DATOS EN LUGARES ESPECIFICADOS POR LOS DE DIRECCION; E) MEDIOS (104) PARA LEER EN SECUENCIA LA MEMORIA DE CONEXION PARA DAR SALIDA A UNA PALABRA DE DATOS; F) MEDIOS MULTIPLEXADORES (110 Y 111) QUE TIENEN UN PAR DE BUSES DE ENTRADA CONECTADOS, UNO PARA RECIBIR SEÑALES DE LA MEMORIA DE DATOS (102), Y OTRO PARA RECIBIR UNA PRIMERA PARTE DE LA PALABRA DE DATOS; G) MEDIOS QUE APLICAN UNA SEGUNDA PARTE DE LA PALABRA DE DATOS A UNA ENTRADA DE CONTROL DEAS DE CONTROL, COMPUESTAS DE BITIOSLOS MEDIOS MULTIPLEXADORES; H) MEDIOS CONVERTIDORES PARALELOS A SERIE PARA RECIBIR SEÑALES DE SALIDA DE LOS MEDIOS MULTIPLEXADORES Y PARA CONVERTIR LAS SEÑALES A UNA FORMA SERIAL PARA ALIMENTACION A UNA PLURALIDAD DE LINEAS DE SALIDA.
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CA000385726A CA1171946A (en) | 1981-09-11 | 1981-09-11 | Time division switching matrix |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| ES8401697A1 true ES8401697A1 (es) | 1983-12-16 |
| ES515618A0 ES515618A0 (es) | 1983-12-16 |
Family
ID=4120929
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| ES515618A Granted ES515618A0 (es) | 1981-09-11 | 1982-09-10 | Perfeccionamientos en una matriz de conmutacion por division de tiempo. |
Country Status (9)
| Country | Link |
|---|---|
| US (1) | US4510597A (es) |
| JP (1) | JPS5856599A (es) |
| CA (1) | CA1171946A (es) |
| DE (1) | DE3232600A1 (es) |
| ES (1) | ES515618A0 (es) |
| FR (1) | FR2513057A1 (es) |
| GB (1) | GB2110507B (es) |
| IT (1) | IT1152394B (es) |
| MX (1) | MX152298A (es) |
Families Citing this family (23)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CA1199394A (en) * | 1983-02-18 | 1986-01-14 | Conrad Lewis | Switching system with separate supervisory links |
| CA1203875A (en) * | 1983-06-16 | 1986-04-29 | Mitel Corporation | Switching system loopback test circuit |
| CA1203876A (en) * | 1983-06-29 | 1986-04-29 | Conrad Lewis | Peripheral control for a digital telephone system |
| JPS61205096A (ja) * | 1985-03-08 | 1986-09-11 | Nippon Telegr & Teleph Corp <Ntt> | 時分割交換方式 |
| GB2182228A (en) * | 1985-10-02 | 1987-05-07 | Gen Electric Plc | Signal handling device |
| JPH0779514B2 (ja) * | 1986-01-24 | 1995-08-23 | 日本電気株式会社 | 時分割時間スイツチ制御方式 |
| CA1254981A (en) * | 1986-02-18 | 1989-05-30 | Lester Kirkland | Communications switching system |
| CA1279393C (en) * | 1987-01-23 | 1991-01-22 | A. David Milton | Digital signal processing system |
| US4805172A (en) * | 1987-04-10 | 1989-02-14 | Redeom Laboratories, Inc. | Time division multiplex (TDM) switching system especially for pulse code modulated (PCM) telephony signals |
| CA1292334C (en) * | 1987-04-28 | 1991-11-19 | Tsuneo Kobayashi | Double-buffered time division switching system |
| US4860281A (en) * | 1988-02-29 | 1989-08-22 | Motorola, Inc. | Individual subchannel loopback in the PCM interfaces of a digital telephone exchange with control of the outbound path |
| US5060227A (en) * | 1988-02-29 | 1991-10-22 | Motorola, Inc. | Digital telephone switch with simultaneous dual PCM format compatibility |
| JPH0564276A (ja) * | 1991-08-30 | 1993-03-12 | Nec Corp | 時間スイツチ回路 |
| EP0585475B1 (de) * | 1992-07-31 | 1998-09-23 | Siemens Aktiengesellschaft | Verfahren zum Laden und Prüfen des Haltespeichers einer Zeitstufe in einem Koppelnetz einer digitalen Zeitmultiplex-Vermittlungsstelle |
| CA2109007C (en) * | 1993-10-22 | 1999-05-04 | Thomas Gray | Time slot assigner for communication system |
| DE19547707A1 (de) * | 1995-12-20 | 1997-07-03 | Thomson Brandt Gmbh | Verfahren, Encoder und Decoder zur Übertragung von hierarchisch in mehrere Teile gegliederten digitalen Signalen |
| US6067296A (en) * | 1997-03-28 | 2000-05-23 | Adtran, Inc. | Parallel backplane architecture providing asymmetric bus time slot cross-connect capability |
| US6570887B2 (en) | 1999-01-22 | 2003-05-27 | Intel Corporation | Method and apparatus employing associative memories to implement message passing |
| US6597690B1 (en) | 1999-01-22 | 2003-07-22 | Intel Corporation | Method and apparatus employing associative memories to implement limited switching |
| US20020176410A1 (en) * | 2001-05-16 | 2002-11-28 | Macadam Dave | Time-slot interchange switches having automatic frame alignment measurement and programming capability |
| US7257115B2 (en) | 2002-07-25 | 2007-08-14 | Integrated Device Technology, Inc. | Data memory address generation for time-slot interchange switches |
| US7266128B1 (en) | 2002-12-06 | 2007-09-04 | Integrated Device Technology, Inc. | Time-slot interchange switches having efficient block programming and on-chip bypass capabilities and methods of operating same |
| GB0317672D0 (en) * | 2003-07-29 | 2003-09-03 | Zarlink Semiconductor Inc | Programmable bit rates in a constant bandwith TDM switch |
Family Cites Families (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE870252C (de) * | 1944-05-13 | 1953-03-12 | Guenther O Dr Schenck | Verfahren zur Darstellung von ª†-Oxocarbonsaeuren |
| NL7307169A (es) * | 1973-05-23 | 1974-11-26 | ||
| NL7701521A (nl) * | 1976-02-17 | 1977-08-19 | Thomson Csf | Symmetrische tijdelijk matrix, alsmede ver- bindingsnetwerk voorzien van een dergelijke matrix. |
| JPS5428516A (en) * | 1977-08-08 | 1979-03-03 | Nippon Telegr & Teleph Corp <Ntt> | Channel converter |
| DE2909762C2 (de) * | 1978-03-17 | 1986-11-13 | International Standard Electric Corp., New York, N.Y. | PCM-Fernmeldevermittlungsanlage |
| US4392221A (en) * | 1979-09-08 | 1983-07-05 | Plessey Overseas Limited | Time division multiplex module for use in digital switching network |
| US4298977A (en) * | 1979-09-10 | 1981-11-03 | Bell Telephone Laboratories, Incorporated | Broadcast and alternate message time slot interchanger |
| JPS5843955B2 (ja) * | 1979-09-20 | 1983-09-30 | 富士通株式会社 | 時分割電子交換機 |
| US4322843A (en) * | 1979-12-26 | 1982-03-30 | Bell Telephone Laboratories, Incorporated | Control information communication arrangement for a time division switching system |
| JPS56122268A (en) * | 1980-02-29 | 1981-09-25 | Nec Corp | Digital signal system for exchange |
| GB2083319B (en) * | 1980-06-25 | 1984-03-28 | Plessey Co Ltd | Digital switching module |
| JPS5730489A (en) * | 1980-07-31 | 1982-02-18 | Fujitsu Ltd | Time-division memory system |
-
1981
- 1981-09-11 CA CA000385726A patent/CA1171946A/en not_active Expired
- 1981-12-03 US US06/327,196 patent/US4510597A/en not_active Expired - Lifetime
-
1982
- 1982-09-02 DE DE19823232600 patent/DE3232600A1/de active Granted
- 1982-09-10 IT IT23213/82A patent/IT1152394B/it active
- 1982-09-10 MX MX194362A patent/MX152298A/es unknown
- 1982-09-10 GB GB08225839A patent/GB2110507B/en not_active Expired
- 1982-09-10 FR FR8215751A patent/FR2513057A1/fr active Pending
- 1982-09-10 ES ES515618A patent/ES515618A0/es active Granted
- 1982-09-11 JP JP57158734A patent/JPS5856599A/ja active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| FR2513057A1 (fr) | 1983-03-18 |
| IT1152394B (it) | 1986-12-31 |
| IT8223213A0 (it) | 1982-09-10 |
| IT8223213A1 (it) | 1984-03-10 |
| CA1171946A (en) | 1984-07-31 |
| US4510597A (en) | 1985-04-09 |
| MX152298A (es) | 1985-06-24 |
| GB2110507A (en) | 1983-06-15 |
| ES515618A0 (es) | 1983-12-16 |
| DE3232600A1 (de) | 1983-03-31 |
| DE3232600C2 (es) | 1989-06-01 |
| GB2110507B (en) | 1985-03-20 |
| JPS5856599A (ja) | 1983-04-04 |
| JPH0141078B2 (es) | 1989-09-01 |
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