ES8501545A1 - Una unidad de control de requrimiento de acceso en un sistema de procesado de datos. - Google Patents

Una unidad de control de requrimiento de acceso en un sistema de procesado de datos.

Info

Publication number
ES8501545A1
ES8501545A1 ES523396A ES523396A ES8501545A1 ES 8501545 A1 ES8501545 A1 ES 8501545A1 ES 523396 A ES523396 A ES 523396A ES 523396 A ES523396 A ES 523396A ES 8501545 A1 ES8501545 A1 ES 8501545A1
Authority
ES
Spain
Prior art keywords
data processing
processing system
control apparatus
access request
request control
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
ES523396A
Other languages
English (en)
Other versions
ES523396A0 (es
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from JP57104736A external-priority patent/JPS58222361A/ja
Priority claimed from JP57108775A external-priority patent/JPS58225463A/ja
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Publication of ES8501545A1 publication Critical patent/ES8501545A1/es
Publication of ES523396A0 publication Critical patent/ES523396A0/es
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/18—Handling requests for interconnection or transfer for access to memory bus based on priority control

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Multi Processors (AREA)
  • Complex Calculations (AREA)

Abstract

UNIDAD DE CONTROL DE REQUERIMIENTO DE ACCESO EN UN SISTEMA DE PROCESADO DE DATOS, EN PARTICULAR, APARATO PARA DETERMINAR UNA PRIORIDAD ENTRE UNA PLURALIDAD DE REQUERIMIENTOS DE ACCESO EN EL APARATO DE CONTROL DE MEMORIA.CONSTA DE UN CIRCUITO DE SELECCION DE REQUERIMIENTO DE ACCESO, CONECTADO CON LA PLURALIDAD DE APARATOS DE REQUERIMIENTO DE ACCESO; DE UN CIRCUITO DE CONTROL DE TUBERIA, CONECTADO CON EL CIRCUITO DE SELECCION DE REQUERIMIENTO DE ACCESO Y CON EL APARATO DE MEMORIA; Y DE UN CIRCUITO DE CONTROL DE PRIORIDAD CONECTADO CON EL CIRCUITO DE CONTROL DE TUBERIA.
ES523396A 1982-06-18 1983-06-17 Una unidad de control de requrimiento de acceso en un sistema de procesado de datos. Granted ES523396A0 (es)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP57104736A JPS58222361A (ja) 1982-06-18 1982-06-18 デ−タ処理システムにおけるアクセス要求の優先順位決定制御方式
JP57108775A JPS58225463A (ja) 1982-06-24 1982-06-24 アクセス処理方式

Publications (2)

Publication Number Publication Date
ES8501545A1 true ES8501545A1 (es) 1984-12-01
ES523396A0 ES523396A0 (es) 1984-12-01

Family

ID=26445142

Family Applications (1)

Application Number Title Priority Date Filing Date
ES523396A Granted ES523396A0 (es) 1982-06-18 1983-06-17 Una unidad de control de requrimiento de acceso en un sistema de procesado de datos.

Country Status (7)

Country Link
EP (1) EP0097499B1 (es)
KR (1) KR860000904B1 (es)
AU (1) AU540649B2 (es)
BR (1) BR8303232A (es)
CA (1) CA1193024A (es)
DE (1) DE3380457D1 (es)
ES (1) ES523396A0 (es)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4788640A (en) * 1986-01-17 1988-11-29 Intel Corporation Priority logic system
CN114281413B (zh) * 2021-12-28 2025-02-07 海光信息技术股份有限公司 流水线冲突处理方法、数据处理装置、电子设备和介质

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB1077339A (en) * 1965-04-05 1967-07-26 Ibm Control device for a data processor
US4152764A (en) * 1977-03-16 1979-05-01 International Business Machines Corporation Floating-priority storage control for processors in a multi-processor system
US4345309A (en) * 1980-01-28 1982-08-17 Digital Equipment Corporation Relating to cached multiprocessor system with pipeline timing

Also Published As

Publication number Publication date
KR840005230A (ko) 1984-11-05
EP0097499B1 (en) 1989-08-23
BR8303232A (pt) 1984-01-31
ES523396A0 (es) 1984-12-01
KR860000904B1 (ko) 1986-07-16
AU540649B2 (en) 1984-11-29
EP0097499A3 (en) 1985-07-31
CA1193024A (en) 1985-09-03
AU1588383A (en) 1983-12-22
EP0097499A2 (en) 1984-01-04
DE3380457D1 (en) 1989-09-28

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Legal Events

Date Code Title Description
FD1A Patent lapsed

Effective date: 19971001