ES8501586A1 - Aparato con auto-verificacion para generar retardos de tiempo - Google Patents

Aparato con auto-verificacion para generar retardos de tiempo

Info

Publication number
ES8501586A1
ES8501586A1 ES524449A ES524449A ES8501586A1 ES 8501586 A1 ES8501586 A1 ES 8501586A1 ES 524449 A ES524449 A ES 524449A ES 524449 A ES524449 A ES 524449A ES 8501586 A1 ES8501586 A1 ES 8501586A1
Authority
ES
Spain
Prior art keywords
time delay
testable time
testable
testing component
stage
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
ES524449A
Other languages
English (en)
Other versions
ES524449A0 (es
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
General Electric Co
Original Assignee
General Electric Co
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by General Electric Co filed Critical General Electric Co
Publication of ES524449A0 publication Critical patent/ES524449A0/es
Publication of ES8501586A1 publication Critical patent/ES8501586A1/es
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
    • H03K5/135—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals by the use of time reference signals, e.g. clock signals
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
    • H03K5/14—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals by the use of delay lines
    • G—PHYSICS
    • G08—SIGNALLING
    • G08C—TRANSMISSION SYSTEMS FOR MEASURED VALUES, CONTROL OR SIMILAR SIGNALS
    • G08C13/00—Arrangements for influencing the relationship between signals at input and output, e.g. differentiating, delaying

Landscapes

  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • General Physics & Mathematics (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Testing And Monitoring For Control Systems (AREA)
  • Monitoring And Testing Of Nuclear Reactors (AREA)
  • Test And Diagnosis Of Digital Computers (AREA)
  • Pulse Circuits (AREA)

Abstract

APARATO CON AUTO-VERIFICACION PARA GENERAR RETARDOS DE TIEMPO.CONSTA DE UN DISPOSITIVO QUE RESPONDE A UNA SEN/AL DE ENTRADA DE FUNCIONAMIENTO GENERANDO UNA SEN/AL DE SALIDA DE FUNCIONAMIENTO CON UN RETARDO DE TIEMPO PREDETERMINADO RESPECTO A DICHA SEN/AL DE ENTRADA; Y DE UN DISPOSITIVO CONECTADO CON DICHO DISPOSITIVO GENERADOR DE RETARDO DE TIEMPO, PARA SUPERVISAR SUSTANCIALMENTE EL FUNCIONAMIENTO DEL MENCIONADO DISPOSITIVO DE RETARDO DE TIEMPO.
ES524449A 1982-07-27 1983-07-26 Aparato con auto-verificacion para generar retardos de tiempo Expired ES8501586A1 (es)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US06/402,323 US4519090A (en) 1982-07-27 1982-07-27 Testable time delay

Publications (2)

Publication Number Publication Date
ES524449A0 ES524449A0 (es) 1984-12-01
ES8501586A1 true ES8501586A1 (es) 1984-12-01

Family

ID=23591437

Family Applications (1)

Application Number Title Priority Date Filing Date
ES524449A Expired ES8501586A1 (es) 1982-07-27 1983-07-26 Aparato con auto-verificacion para generar retardos de tiempo

Country Status (7)

Country Link
US (1) US4519090A (es)
JP (1) JPS5963000A (es)
KR (1) KR840005625A (es)
DE (1) DE3325362C2 (es)
ES (1) ES8501586A1 (es)
IT (1) IT1170168B (es)
SE (1) SE8304114L (es)

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4789835A (en) * 1983-08-01 1988-12-06 Fairchild Camera & Instrument Corporation Control of signal timing apparatus in automatic test systems using minimal memory
US4849702A (en) * 1983-08-01 1989-07-18 Schlumberger Techologies, Inc. Test period generator for automatic test equipment
AU572593B2 (en) * 1983-12-22 1988-05-12 Alcatel N.V. Signal recognition system
US4757523A (en) * 1984-08-02 1988-07-12 Texas Instruments Incorporated High speed testing of integrated circuit
US4649537A (en) * 1984-10-22 1987-03-10 Westinghouse Electric Corp. Random pattern lock and key fault detection scheme for microprocessor systems
US4982412A (en) * 1989-03-13 1991-01-01 Moore Push-Pin Company Apparatus and method for counting a plurality of similar articles
DE4142775C2 (de) * 1991-12-23 1994-10-06 Telefunken Microelectron Verfahren zum Überprüfen eines in einem Schaltkreis integrierten Zeitglieds
US5497475A (en) * 1993-02-05 1996-03-05 National Semiconductor Corporation Configurable integrated circuit having true and shadow EPROM registers
US5473651A (en) * 1994-12-28 1995-12-05 At&T Corp. Method and apparatus for testing large embedded counters
US6889349B2 (en) * 2001-08-22 2005-05-03 Hewlett-Packard Development Company, L.P. Digital event sampling circuit and method
EP1748299B1 (de) * 2005-07-29 2008-03-19 Siemens Aktiengesellschaft Elektronische Schaltung, System mit einer elektronischen Schaltung und Verfahren zum Testen einer elektronischen Schaltung
CN111624469B (zh) * 2020-06-24 2025-05-06 苏州纳芯微电子股份有限公司 数字隔离器的传播延时测试电路

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3845282A (en) * 1972-09-01 1974-10-29 Kearney & Trecker Corp Apparatus and method for unambiguous counter reading
US3934131A (en) * 1975-01-06 1976-01-20 The Unites States Of America As Represented By The Secretary Of The Navy Output controller for initiating delayed or conditional commands via a general purpose computer
US4082218A (en) * 1976-12-27 1978-04-04 Burroughs Corporation Potential failure detecting circuit having improved means for detecting transitions in short duration signals
FR2390856A1 (fr) * 1977-05-10 1978-12-08 Lannionnais Electronique Base de temps
US4144448A (en) * 1977-11-29 1979-03-13 International Business Machines Corporation Asynchronous validity checking system and method for monitoring clock signals on separate electrical conductors
US4223213A (en) * 1978-05-22 1980-09-16 Mcneil Akron, Inc. Apparatus for rapid data verification of a programmable timer
US4336448A (en) * 1980-04-18 1982-06-22 General Motors Corporation Binary counter and circuit for testing same
US4373201A (en) * 1980-11-28 1983-02-08 Honeywell Inc. Fail safe digital timer
DE3126747C2 (de) * 1981-07-01 1983-06-01 Licentia Patent-Verwaltungs-Gmbh, 6000 Frankfurt Schaltungsanordnung zur Anpassung der Länge eintreffender Impulse
US4392226A (en) * 1981-09-28 1983-07-05 Ncr Corporation Multiple source clock encoded communications error detection circuit

Also Published As

Publication number Publication date
US4519090A (en) 1985-05-21
KR840005625A (ko) 1984-11-14
SE8304114D0 (sv) 1983-07-22
DE3325362C2 (de) 1985-04-18
ES524449A0 (es) 1984-12-01
IT1170168B (it) 1987-06-03
IT8322043A0 (it) 1983-07-13
SE8304114L (sv) 1984-01-28
JPS5963000A (ja) 1984-04-10
DE3325362A1 (de) 1984-02-23

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