ES8507273A1 - Perfeccionamientos en los dispositivos para entrada de datos de direccion en un circuito integrado - Google Patents

Perfeccionamientos en los dispositivos para entrada de datos de direccion en un circuito integrado

Info

Publication number
ES8507273A1
ES8507273A1 ES536539A ES536539A ES8507273A1 ES 8507273 A1 ES8507273 A1 ES 8507273A1 ES 536539 A ES536539 A ES 536539A ES 536539 A ES536539 A ES 536539A ES 8507273 A1 ES8507273 A1 ES 8507273A1
Authority
ES
Spain
Prior art keywords
interface
circuit
pins
address
pin
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
ES536539A
Other languages
English (en)
Other versions
ES536539A0 (es
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Essex Solutions USA LLC
Original Assignee
Essex Group LLC
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Essex Group LLC filed Critical Essex Group LLC
Publication of ES536539A0 publication Critical patent/ES536539A0/es
Publication of ES8507273A1 publication Critical patent/ES8507273A1/es
Expired legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/44—Arrangements for executing specific programs
    • G06F9/4401—Bootstrapping
    • G06F9/4403—Processor initialisation
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/22—Means for limiting or controlling the pin/gate ratio
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/24—Resetting means

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Software Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Security & Cryptography (AREA)
  • Bus Control (AREA)
  • Small-Scale Networks (AREA)
  • Logic Circuits (AREA)

Abstract

PERFECCIONAMIENTOS EN LOS DISPOSITIVOS PARA ENTRADA DE DATOS DE DIRECCION EN UN CIRCUITO INTEGRADO.CONSISTENTES EN: UN CIRCUITO INTEGRADO CON UNA SERIE DE PRIMERAS PATILLAS IÑO SEPARADAS EN LA INTERFASE INTERNA/EXTERNA DEL CIRCUITO, QUE TIENEN ELEMENTOS DE SALIDA DEL CIRCUITO Y ORGANOS DE DIRECCION DEL CIRCUITO CONECTADOS A LAS MISMAS Y COLOCADOS INTERIORMENTE A LA INTERFASE; UNA PATILLA IÑO ADICIONAL A LA INTERFASE; UN CONDUCTOR COMUN, CONECTADO A LA PATILLA IÑO ADICIONAL Y COLOCADO EXTERIORMENTE A LA INTERFASE; UNOS ELEMENTOS UNIDIRECCIONALES DE CONDUCCION DE DIRECCIONES COLOCADOS EN LA PARTE EXTERNA DE LA INTERFASE Y CONECTADOS INDIVIDUALMENTE A UN MISMO EXTREMO CORRESPONDIENTE DE LAS PRIMERAS PATILLAS IÑO Y AL OTRO EXTREMO DEL CONDUCTOR COMUN; UNOS ELEMENTOS DE CONTROL DE NIVEL CONECTADOS A LA PATILLA IÑO ADICIONAL; UNOS SUMINISTRADORES DE LA SEN/AL DE SELECCION A LOS CITADOS ELEMENTOS DE CONTROL DE NIVEL, Y UNOS ALMACENADORES DE LOS BITS DE DIRECCION EN LOS CIRCUITOS DE DIRECCION.
ES536539A 1983-10-07 1984-10-05 Perfeccionamientos en los dispositivos para entrada de datos de direccion en un circuito integrado Expired ES8507273A1 (es)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US06/540,573 US4628480A (en) 1983-10-07 1983-10-07 Arrangement for optimized utilization of I/O pins

Publications (2)

Publication Number Publication Date
ES536539A0 ES536539A0 (es) 1985-09-16
ES8507273A1 true ES8507273A1 (es) 1985-09-16

Family

ID=24156024

Family Applications (1)

Application Number Title Priority Date Filing Date
ES536539A Expired ES8507273A1 (es) 1983-10-07 1984-10-05 Perfeccionamientos en los dispositivos para entrada de datos de direccion en un circuito integrado

Country Status (6)

Country Link
US (1) US4628480A (es)
EP (1) EP0141769B1 (es)
JP (1) JPS60144854A (es)
CA (1) CA1216367A (es)
DE (1) DE3477970D1 (es)
ES (1) ES8507273A1 (es)

Families Citing this family (48)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4719598A (en) * 1985-05-31 1988-01-12 Harris Corporation Bit addressable programming arrangement
JPS63132303A (ja) * 1986-11-24 1988-06-04 Mitsubishi Electric Corp 車載用マイクロコンピユ−タ応用制御装置
GB2198564A (en) * 1986-12-12 1988-06-15 Philips Electronic Associated Data port selection
US5218707A (en) * 1988-10-28 1993-06-08 Dallas Semiconductor Corp. Integrated circuit with remappable interrupt pins
US5175845A (en) * 1988-12-09 1992-12-29 Dallas Semiconductor Corp. Integrated circuit with watchdog timer and sleep control logic which places IC and watchdog timer into sleep mode
US5590343A (en) * 1988-12-09 1996-12-31 Dallas Semiconductor Corporation Touch-sensitive switching circuitry for power-up
US5243700A (en) * 1988-12-30 1993-09-07 Larsen Robert E Port expander architecture for mapping a first set of addresses to external memory and mapping a second set of addresses to an I/O port
GB2227582B (en) * 1988-12-30 1992-11-04 Intel Corp Port expander architecture for eprom
US5121487A (en) * 1989-02-21 1992-06-09 Sun Microsystems, Inc. High speed bus with virtual memory data transfer capability using virtual address/data lines
US5084637A (en) * 1989-05-30 1992-01-28 International Business Machines Corp. Bidirectional level shifting interface circuit
JP2880547B2 (ja) * 1990-01-19 1999-04-12 三菱電機株式会社 半導体記憶装置
US5247450A (en) * 1991-02-12 1993-09-21 Vhc Ltd. Electronic timing system for glassware-forming machines
US5224072A (en) * 1991-04-04 1993-06-29 Oki Electric Industry Co., Ltd. Read-only memory with few programming signal lines
US5533200A (en) * 1994-03-18 1996-07-02 Intel Corporation Method and apparatus for transmission of signals over a shared line
US5701515A (en) * 1994-06-16 1997-12-23 Apple Computer, Inc. Interface for switching plurality of pin contacts to transmit data line and plurality of pin contacts to receive data line to interface with serial controller
US5553070A (en) * 1994-09-13 1996-09-03 Riley; Robert E. Data link module for time division multiplexing control systems
US6359547B1 (en) 1994-11-15 2002-03-19 William D. Denison Electronic access control device
FR2739949B1 (fr) * 1995-10-13 1997-11-14 Aeg Schneider Automation Circuit electronique configurable
US5860028A (en) * 1996-02-01 1999-01-12 Paragon Electric Company, Inc. I/O bus expansion system wherein processor checks plurality of possible address until a response from the peripheral selected by address decoder using user input
DE69618344T2 (de) * 1996-06-06 2002-08-14 Stmicroelectronics S.R.L., Agrate Brianza Schaltung um redundante Daten einer Redundanzschaltung innerhalb einer Speicheranordnung durch zeitgeteilte Annäherung zu übertragen
EP0811918B1 (en) * 1996-06-06 2002-01-30 STMicroelectronics S.r.l. Semiconductor memory device with clocked column redundancy and time-shared redundancy data transfer approach
US5864663A (en) * 1996-09-12 1999-01-26 United Technologies Corporation Selectively enabled watchdog timer circuit
US6026453A (en) * 1997-07-15 2000-02-15 International Business Machines Corporation System for facilitating serial data communications utilizing number of cycles input signal remained asserted to indicate data output logical state
US6598105B1 (en) * 1999-04-13 2003-07-22 Microsoft Corporation Interrupt arbiter for a computing system
US7596139B2 (en) 2000-11-17 2009-09-29 Foundry Networks, Inc. Backplane interface adapter with error control and redundant fabric
US7236490B2 (en) 2000-11-17 2007-06-26 Foundry Networks, Inc. Backplane interface adapter
US7468975B1 (en) 2002-05-06 2008-12-23 Foundry Networks, Inc. Flexible method for processing data packets in a network routing system for enhanced efficiency and monitoring capability
US7187687B1 (en) 2002-05-06 2007-03-06 Foundry Networks, Inc. Pipeline method and system for switching packets
US20120155466A1 (en) 2002-05-06 2012-06-21 Ian Edward Davis Method and apparatus for efficiently processing data packets in a computer network
US6901072B1 (en) 2003-05-15 2005-05-31 Foundry Networks, Inc. System and method for high speed packet transmission implementing dual transmit and receive pipelines
US7817659B2 (en) 2004-03-26 2010-10-19 Foundry Networks, Llc Method and apparatus for aggregating input data streams
US8730961B1 (en) 2004-04-26 2014-05-20 Foundry Networks, Llc System and method for optimizing router lookup
US7657703B1 (en) 2004-10-29 2010-02-02 Foundry Networks, Inc. Double density content addressable memory (CAM) lookup scheme
US8448162B2 (en) 2005-12-28 2013-05-21 Foundry Networks, Llc Hitless software upgrades
US7979168B2 (en) 2006-07-25 2011-07-12 Silicon Laboratories Inc. Powered device including a multi-use detection resistor
US7903654B2 (en) 2006-08-22 2011-03-08 Foundry Networks, Llc System and method for ECMP load sharing
US8238255B2 (en) 2006-11-22 2012-08-07 Foundry Networks, Llc Recovering from failures without impact on data traffic in a shared bus architecture
US8395996B2 (en) 2007-01-11 2013-03-12 Foundry Networks, Llc Techniques for processing incoming failure detection protocol packets
US8271859B2 (en) * 2007-07-18 2012-09-18 Foundry Networks Llc Segmented CRC design in high speed networks
US8037399B2 (en) 2007-07-18 2011-10-11 Foundry Networks, Llc Techniques for segmented CRC design in high speed networks
US8149839B1 (en) 2007-09-26 2012-04-03 Foundry Networks, Llc Selection of trunk ports and paths using rotation
US7804859B2 (en) * 2008-06-30 2010-09-28 Silicon Laboratories, Inc. System and method of providing electrical isolation
US8095710B2 (en) * 2008-06-30 2012-01-10 Silicon Laboratories Inc. System and method of providing electrical isolation
US8090901B2 (en) 2009-05-14 2012-01-03 Brocade Communications Systems, Inc. TCAM management approach that minimize movements
US8599850B2 (en) 2009-09-21 2013-12-03 Brocade Communications Systems, Inc. Provisioning single or multistage networks using ethernet service instances (ESIs)
DE102011079688A1 (de) * 2010-08-03 2012-04-05 Continental Teves Ag & Co. Ohg Kommunikationsverfahren mit Echo
KR101531090B1 (ko) * 2013-06-28 2015-06-23 삼성전기주식회사 오동작 방지 기능을 갖는 ic 장치 및 ic 장치의 오동작 방지 방법
CN116578512A (zh) * 2023-03-31 2023-08-11 上海矽力杰微电子技术有限公司 地址扩展电路和应用其的通讯接口芯片

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS52130536A (en) * 1976-04-26 1977-11-01 Toshiba Corp Semiconductor memory unit
EP0009862B1 (en) * 1978-09-05 1982-09-15 Motorola, Inc. Programmable mode of operation select by reset and data processor using this select
JPS5951073B2 (ja) * 1980-03-27 1984-12-12 富士通株式会社 半導体記憶装置
JPS5717048A (en) * 1980-07-07 1982-01-28 Nippon Telegr & Teleph Corp <Ntt> Time-division information output system of data transfer circuit
US4495603A (en) * 1980-07-31 1985-01-22 Varshney Ramesh C Test system for segmented memory
CA1163721A (en) * 1980-08-18 1984-03-13 Milan Slamka Apparatus for the dynamic in-circuit testing of electronic digital circuit elements
US4434474A (en) * 1981-05-15 1984-02-28 Rockwell International Corporation Single pin time-sharing for serially inputting and outputting data from state machine register apparatus
JPS57196334A (en) * 1981-05-26 1982-12-02 Toshiba Corp Memory interface
JPS58139226A (ja) * 1982-02-12 1983-08-18 Nec Corp 大規模集積回路における初期値設定方式

Also Published As

Publication number Publication date
EP0141769A2 (en) 1985-05-15
EP0141769A3 (en) 1985-06-12
DE3477970D1 (en) 1989-06-01
ES536539A0 (es) 1985-09-16
JPS60144854A (ja) 1985-07-31
EP0141769B1 (en) 1989-04-26
US4628480A (en) 1986-12-09
JPH0473180B2 (es) 1992-11-20
CA1216367A (en) 1987-01-06

Similar Documents

Publication Publication Date Title
ES8507273A1 (es) Perfeccionamientos en los dispositivos para entrada de datos de direccion en un circuito integrado
ES2026136T3 (es) Tarjeta que comprende un componente y un micromodulo con contactos de flanco.
ES526020A0 (es) Una pastilla de circuito logico digital integrado
ATE90162T1 (de) Datenverarbeitungssystem mit einer steckbaren optionellen karte.
KR850008017A (ko) Cmos 입출력회로
ATE65652T1 (de) Programmierbares logisches speicherelement fuer programmierbare logische einrichtungen.
KR900008526A (ko) 반도체 기억장치
KR970071288A (ko) 메모리 시스템 및 그것에 이용되는 반도체 기억 장치
GB2097621B (en) Semiconductor memory devices
KR880004478A (ko) 반도체 기억장치
KR850008566A (ko) 대치용장 회로를 가진 반도체집적 회로
KR930003137A (ko) 멀티 포드 ram용 메모리셀
KR910008730A (ko) 반도체 기억장치
KR900008520A (ko) 불휘발성 메모리
KR910007128A (ko) 프로그램가능 논리 집적회로소자와 이를 위한 전원장치 및 전원공급 방법
KR860006875A (ko) 반도체 장치
ATE30085T1 (de) Rechnerkopplung.
KR960012497A (ko) 반도체 집적회로
KR830008565A (ko) 에미터 기능논리래로된 카운터 회로
KR960026651A (ko) 퓨징 시스템
KR900002311A (ko) 캐시메모리 및 그 캐시메모리가 채용된 억세스제어장치
EP0013885A3 (en) Parity check device for a register array
KR900006797Y1 (ko) 데이타 카운트회로
JPH0350905A (ja) トランジスタ回路
KR910001598A (ko) 메모리 카드 유닛을 가진 휴대형 전자 장치

Legal Events

Date Code Title Description
FD1A Patent lapsed

Effective date: 19970519