ES8900206A1 - Sistema de interconexion entre un ordenador central y un controlador de disco. - Google Patents

Sistema de interconexion entre un ordenador central y un controlador de disco.

Info

Publication number
ES8900206A1
ES8900206A1 ES552765A ES552765A ES8900206A1 ES 8900206 A1 ES8900206 A1 ES 8900206A1 ES 552765 A ES552765 A ES 552765A ES 552765 A ES552765 A ES 552765A ES 8900206 A1 ES8900206 A1 ES 8900206A1
Authority
ES
Spain
Prior art keywords
bus
control
signal lines
internal
controllable
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
ES552765A
Other languages
English (en)
Other versions
ES552765A0 (es
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nokia Spain SA
Original Assignee
Alcatel Standard Electrics SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Alcatel Standard Electrics SA filed Critical Alcatel Standard Electrics SA
Publication of ES8900206A1 publication Critical patent/ES8900206A1/es
Publication of ES552765A0 publication Critical patent/ES552765A0/es
Expired legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
    • G06F3/0671—In-line storage system
    • G06F3/0673—Single storage device

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Human Computer Interaction (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Bus Control (AREA)
  • Signal Processing For Digital Recording And Reproducing (AREA)

Abstract

DISPOSITIVO DE INTERCONEXION PARA CONTROL DE TRANSFERENCIA ENTRE UN ORDENADOR CENTRAL Y UN CONTROLADOR DE DISCO. ESTA CARACTERIZADO POR CONTENER LOS BUSES INTERNOS INTERCONECTADOS VIA BUFFERS PARA CONTROLAR LAS DIRECCIONES DE TRANSFERENCIA, DOS BUFFERS CONTROLABLES CONECTADOS A LOS BUSES DE DIRECCION. UN CONTROLADOR DE INTERCONEXION A DONDE SE CONECTAN: EL BUS DE DIRECCIONES Y LAS 3 PRIMERAS LINEAS DE SEÑAL DE CONTROL. AL SEGUNDO GENERADOR DE BIT DE CHEQUEO ESTAN CONECTADOS LA TERCERA Y CUARTA LINEA DE SEÑAL DE CONTROL Y UNA LINEA DE SEÑAL DE ERROR. LOS ESTADOS DE CONTROLADOR DEL DISCO SE CONOCEN MEDIANTE UNA PALABRA DE ESTADO TRANSFERIDA POR LAS LINEAS DE SEÑAL DE CONTROL. EL PRIMER Y SEGUNDO GENERADOR DEL BIT DE CHEQUEO CONECTADOS POR MEDIO DE BUFFER CONTROLABLE: ENLAZADO AL CONTROLADOR DE DISCO POR UNA LINEA DE BIT DE CHEQUEO. EL CONTROLADOR DE INTERCONEXION CONECTADO A LOS BUFFERS POR LINEAS DE SEÑAL DE CONTROL.
ES552765A 1985-03-07 1986-03-07 Sistema de interconexion entre un ordenador central y un controlador de disco. Expired ES8900206A1 (es)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
DE19853508048 DE3508048A1 (de) 1985-03-07 1985-03-07 Schnittstelleneinrichtung

Publications (2)

Publication Number Publication Date
ES8900206A1 true ES8900206A1 (es) 1989-03-16
ES552765A0 ES552765A0 (es) 1989-03-16

Family

ID=6264432

Family Applications (1)

Application Number Title Priority Date Filing Date
ES552765A Expired ES8900206A1 (es) 1985-03-07 1986-03-07 Sistema de interconexion entre un ordenador central y un controlador de disco.

Country Status (5)

Country Link
US (1) US4779196A (es)
EP (1) EP0195309B1 (es)
JP (1) JPS61251950A (es)
DE (2) DE3508048A1 (es)
ES (1) ES8900206A1 (es)

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5033049A (en) * 1989-06-12 1991-07-16 International Business Machines Corporation On-board diagnostic sub-system for SCSI interface
JP2780821B2 (ja) * 1989-09-22 1998-07-30 株式会社日立製作所 オンライン中のダンプ方式およびディスクサブシステム
US5430847A (en) * 1992-10-22 1995-07-04 International Business Machines Corporation Method and system for extending system buses to external devices
JP3433978B2 (ja) * 1993-07-30 2003-08-04 富士通株式会社 入出力制御装置
US5557740A (en) * 1995-05-30 1996-09-17 International Business Machines Corporation Method and system for providing device support testing for a plurality of operating systems
US6871251B1 (en) * 2000-05-17 2005-03-22 Marvell International Ltd. High latency interface between hardware components
US7389374B1 (en) 2000-05-17 2008-06-17 Marvell International Ltd. High latency interface between hardware components
US7281065B1 (en) 2000-08-17 2007-10-09 Marvell International Ltd. Long latency interface protocol
US7840900B1 (en) * 2009-04-30 2010-11-23 Spansion Llc Replacing reset pin in buses while guaranteeing system recovery
US20110093848A1 (en) * 2009-10-19 2011-04-21 International Business Machines Corporation System for improving a user-space environment
US8607039B2 (en) 2010-08-17 2013-12-10 International Business Machines Corporation Isolation of device namespace to allow duplicate/common names in root volume group workload partitions

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3810105A (en) * 1967-10-26 1974-05-07 Xerox Corp Computer input-output system
US3839630A (en) * 1971-12-27 1974-10-01 Hewlett Packard Co Programmable calculator employing algebraic language
US4228496A (en) * 1976-09-07 1980-10-14 Tandem Computers Incorporated Multiprocessor system
US4258418A (en) * 1978-12-28 1981-03-24 International Business Machines Corporation Variable capacity data buffer system
US4380047A (en) * 1980-11-24 1983-04-12 Corvus Systems, Inc. Interface apparatus employing a video tape drive to back-up a disc drive and including error detecting and correcting circuitry
US4433377A (en) * 1981-06-29 1984-02-21 Eustis Mary S Data processing with format varying
US4500958A (en) * 1982-04-21 1985-02-19 Digital Equipment Corporation Memory controller with data rotation arrangement
US4535404A (en) * 1982-04-29 1985-08-13 Honeywell Information Systems Inc. Method and apparatus for addressing a peripheral interface by mapping into memory address space
US4464718A (en) * 1982-07-30 1984-08-07 International Business Machines Corporation Associative file processing method and apparatus
US4543628A (en) * 1983-01-28 1985-09-24 Digital Equipment Corporation Bus for data processing system with fault cycle operation
US4716523A (en) * 1985-06-14 1987-12-29 International Business Machines Corporation Multiple port integrated DMA and interrupt controller and arbitrator

Also Published As

Publication number Publication date
DE3689381D1 (de) 1994-01-27
EP0195309B1 (de) 1993-12-15
EP0195309A3 (en) 1990-05-02
EP0195309A2 (de) 1986-09-24
JPS61251950A (ja) 1986-11-08
DE3508048A1 (de) 1986-09-11
US4779196A (en) 1988-10-18
ES552765A0 (es) 1989-03-16

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Legal Events

Date Code Title Description
FD1A Patent lapsed

Effective date: 19980102