FR1034099A - Perfectionnements apportés aux circuits calculateurs - Google Patents

Perfectionnements apportés aux circuits calculateurs

Info

Publication number
FR1034099A
FR1034099A FR1034099DA FR1034099A FR 1034099 A FR1034099 A FR 1034099A FR 1034099D A FR1034099D A FR 1034099DA FR 1034099 A FR1034099 A FR 1034099A
Authority
FR
France
Prior art keywords
computer circuits
circuits
computer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
Other languages
English (en)
Inventor
Francois-Henri Raymond
Roger-Robert Dussine
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Societe dElectronique et dAutomatisme SA
Original Assignee
Societe dElectronique et dAutomatisme SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Societe dElectronique et dAutomatisme SA filed Critical Societe dElectronique et dAutomatisme SA
Application granted granted Critical
Publication of FR1034099A publication Critical patent/FR1034099A/fr
Expired legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/50—Adding; Subtracting
    • G06F7/504—Adding; Subtracting in bit-serial fashion, i.e. having a single digit-handling circuit treating all denominations after each other

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Pure & Applied Mathematics (AREA)
  • Mathematical Analysis (AREA)
  • Computational Mathematics (AREA)
  • Computing Systems (AREA)
  • Mathematical Optimization (AREA)
  • General Engineering & Computer Science (AREA)
  • Complex Calculations (AREA)
  • Electrotherapy Devices (AREA)
  • Video Image Reproduction Devices For Color Tv Systems (AREA)
FR1034099D 1951-03-17 1951-03-17 Perfectionnements apportés aux circuits calculateurs Expired FR1034099A (fr)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR1018657X 1951-03-17

Publications (1)

Publication Number Publication Date
FR1034099A true FR1034099A (fr) 1953-07-17

Family

ID=9575163

Family Applications (1)

Application Number Title Priority Date Filing Date
FR1034099D Expired FR1034099A (fr) 1951-03-17 1951-03-17 Perfectionnements apportés aux circuits calculateurs

Country Status (4)

Country Link
US (1) US2894687A (fr)
DE (1) DE1018657B (fr)
FR (1) FR1034099A (fr)
GB (1) GB741418A (fr)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US2899133A (en) * 1959-08-11 Inputs
US2920825A (en) * 1955-06-23 1960-01-12 Sperry Rand Corp Binary subtracter
US2920824A (en) * 1955-06-03 1960-01-12 Sperry Rand Corp Binary adder
US2926851A (en) * 1952-12-09 1960-03-01 Int Standard Electric Corp Binary adder-subtracter

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3022951A (en) * 1957-05-14 1962-02-27 Ibm Full adder
NL135486C (fr) * 1958-10-03
US3075093A (en) * 1960-12-19 1963-01-22 Ibm Exclusive or circuit using nor logic

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
NL150648B (nl) * 1948-12-23 Thomson Houston Comp Francaise Schakelinrichting voor het omschakelen van een uitgangskanaal van de ene naar de andere televisiesignaalbron.
GB705478A (en) * 1949-01-17 1954-03-17 Nat Res Dev Electronic computing circuits
GB685218A (en) * 1949-12-23 1952-12-31 Nat Res Dev Improvements in or relating to electronic digital computing devices
US2803401A (en) * 1950-10-10 1957-08-20 Hughes Aircraft Co Arithmetic units for digital computers
US2600744A (en) * 1950-10-21 1952-06-17 Eckert Mauchly Comp Corp Signal responsive apparatus
US2646501A (en) * 1950-10-21 1953-07-21 Eckert Mauchly Comp Corp Signal responsive device
US2590950A (en) * 1950-11-16 1952-04-01 Eckert Mauchly Comp Corp Signal responsive circuit
FR1029204A (fr) * 1950-12-07 1953-06-01 Electronique & Automatisme Sa Dispositifs pour l'addition et la soustraction de nombres
US2596199A (en) * 1951-02-19 1952-05-13 Bell Telephone Labor Inc Error correction in sequential code pulse transmission

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US2899133A (en) * 1959-08-11 Inputs
US2926851A (en) * 1952-12-09 1960-03-01 Int Standard Electric Corp Binary adder-subtracter
US2920824A (en) * 1955-06-03 1960-01-12 Sperry Rand Corp Binary adder
US2920825A (en) * 1955-06-23 1960-01-12 Sperry Rand Corp Binary subtracter

Also Published As

Publication number Publication date
DE1018657B (de) 1957-10-31
US2894687A (en) 1959-07-14
GB741418A (en) 1955-12-07

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