FR1149120A - Circuit de multiplication - Google Patents

Circuit de multiplication

Info

Publication number
FR1149120A
FR1149120A FR1149120DA FR1149120A FR 1149120 A FR1149120 A FR 1149120A FR 1149120D A FR1149120D A FR 1149120DA FR 1149120 A FR1149120 A FR 1149120A
Authority
FR
France
Prior art keywords
multiplication circuit
multiplication
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
Other languages
English (en)
Inventor
Andre-Edouard-Joseph Chatelon
Pierre Seneque
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Laboratoire Central de Telecommunications SA
Original Assignee
Laboratoire Central de Telecommunications SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Laboratoire Central de Telecommunications SA filed Critical Laboratoire Central de Telecommunications SA
Application granted granted Critical
Publication of FR1149120A publication Critical patent/FR1149120A/fr
Expired legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/52—Multiplying; Dividing
    • G06F7/523—Multiplying only
    • G06F7/527—Multiplying only in serial-parallel fashion, i.e. one operand being entered serially and the other in parallel
    • G06F7/5272—Multiplying only in serial-parallel fashion, i.e. one operand being entered serially and the other in parallel with row wise addition of partial products

Landscapes

  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computational Mathematics (AREA)
  • Mathematical Analysis (AREA)
  • Mathematical Optimization (AREA)
  • Pure & Applied Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
FR1149120D 1954-12-31 1954-12-31 Circuit de multiplication Expired FR1149120A (fr)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR1149120T 1954-12-31

Publications (1)

Publication Number Publication Date
FR1149120A true FR1149120A (fr) 1957-12-20

Family

ID=9646637

Family Applications (1)

Application Number Title Priority Date Filing Date
FR1149120D Expired FR1149120A (fr) 1954-12-31 1954-12-31 Circuit de multiplication

Country Status (1)

Country Link
FR (1) FR1149120A (fr)

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