FR2303379A1 - Procede de fabrication de dispositifs a couches multiples ne comportant qu'une seule etape de masquage critique - Google Patents

Procede de fabrication de dispositifs a couches multiples ne comportant qu'une seule etape de masquage critique

Info

Publication number
FR2303379A1
FR2303379A1 FR7601477A FR7601477A FR2303379A1 FR 2303379 A1 FR2303379 A1 FR 2303379A1 FR 7601477 A FR7601477 A FR 7601477A FR 7601477 A FR7601477 A FR 7601477A FR 2303379 A1 FR2303379 A1 FR 2303379A1
Authority
FR
France
Prior art keywords
devices including
masking step
layer devices
manufacturing multi
single critical
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
FR7601477A
Other languages
English (en)
Other versions
FR2303379B1 (fr
Inventor
Kie Y Ahn
Michael Hatzakis
John V Powers
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Publication of FR2303379A1 publication Critical patent/FR2303379A1/fr
Application granted granted Critical
Publication of FR2303379B1 publication Critical patent/FR2303379B1/fr
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01F—MAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
    • H01F41/00—Apparatus or processes specially adapted for manufacturing or assembling magnets, inductances or transformers; Apparatus or processes specially adapted for manufacturing materials characterised by their magnetic properties
    • H01F41/32—Apparatus or processes specially adapted for manufacturing or assembling magnets, inductances or transformers; Apparatus or processes specially adapted for manufacturing materials characterised by their magnetic properties for applying conductive, insulating or magnetic material on a magnetic film, specially adapted for a thin magnetic film
    • H01F41/34—Apparatus or processes specially adapted for manufacturing or assembling magnets, inductances or transformers; Apparatus or processes specially adapted for manufacturing materials characterised by their magnetic properties for applying conductive, insulating or magnetic material on a magnetic film, specially adapted for a thin magnetic film in patterns, e.g. by lithography
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/22—Secondary treatment of printed circuits
    • H05K3/24—Reinforcing of the conductive pattern
    • H05K3/243—Reinforcing of the conductive pattern characterised by selective plating, e.g. for finish plating of pads
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/40—Formation of materials, e.g. in the shape of layers or pillars of conductive or resistive materials
    • H10P14/412—Deposition of metallic or metal-silicide materials
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/05—Patterning and lithography; Masks; Details of resist
    • H05K2203/0562—Details of resist
    • H05K2203/0574—Stacked resist layers used for different processes
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
    • H05K3/108—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern by semi-additive methods; masks therefor
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/38—Improvement of the adhesion between the insulating substrate and the metal
    • H05K3/388—Improvement of the adhesion between the insulating substrate and the metal by the use of a metallic or inorganic thin film adhesion layer

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Thin Magnetic Films (AREA)
  • Hall/Mr Elements (AREA)
  • Electroplating Methods And Accessories (AREA)
  • Magnetic Heads (AREA)
FR7601477A 1975-03-05 1976-01-14 Procede de fabrication de dispositifs a couches multiples ne comportant qu'une seule etape de masquage critique Granted FR2303379A1 (fr)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US05/555,645 US3957552A (en) 1975-03-05 1975-03-05 Method for making multilayer devices using only a single critical masking step

Publications (2)

Publication Number Publication Date
FR2303379A1 true FR2303379A1 (fr) 1976-10-01
FR2303379B1 FR2303379B1 (fr) 1978-05-19

Family

ID=24218066

Family Applications (1)

Application Number Title Priority Date Filing Date
FR7601477A Granted FR2303379A1 (fr) 1975-03-05 1976-01-14 Procede de fabrication de dispositifs a couches multiples ne comportant qu'une seule etape de masquage critique

Country Status (7)

Country Link
US (1) US3957552A (fr)
JP (1) JPS5816548B2 (fr)
CA (1) CA1071761A (fr)
DE (1) DE2555299A1 (fr)
FR (1) FR2303379A1 (fr)
GB (1) GB1522004A (fr)
IT (1) IT1056759B (fr)

Families Citing this family (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS588579B2 (ja) * 1975-08-20 1983-02-16 松下電器産業株式会社 ハンドウタイソウチノセイゾウホウホウ
US4172758A (en) * 1975-11-07 1979-10-30 Rockwell International Corporation Magnetic bubble domain device fabrication technique
US4088490A (en) * 1976-06-14 1978-05-09 International Business Machines Corporation Single level masking process with two positive photoresist layers
US4272348A (en) * 1978-11-20 1981-06-09 International Business Machines Corporation Bubble device fabrication
US4226691A (en) * 1978-11-24 1980-10-07 National Semiconductor Corporation Bubble memory process using an aluminum plus water chemical reaction
US4229248A (en) * 1979-04-06 1980-10-21 Intel Magnetics, Inc. Process for forming bonding pads on magnetic bubble devices
US4328298A (en) * 1979-06-27 1982-05-04 The Perkin-Elmer Corporation Process for manufacturing lithography masks
US4251621A (en) * 1979-11-13 1981-02-17 Bell Telephone Laboratories, Incorporated Selective metal etching of two gold alloys on common surface for semiconductor contacts
US4299680A (en) * 1979-12-31 1981-11-10 Texas Instruments Incorporated Method of fabricating magnetic bubble memory device having planar overlay pattern of magnetically soft material
US4334951A (en) * 1980-03-12 1982-06-15 Bell Telephone Laboratories, Incorporated Fabrication technique for the production of devices which depend on magnetic bubbles
DE3016050C2 (de) * 1980-04-25 1985-08-29 Siemens AG, 1000 Berlin und 8000 München Verfahren zur Herstellung von Fotolackstrukturen für integrierte Halbleiterschaltungsanordnungen
US4325181A (en) * 1980-12-17 1982-04-20 The United States Of America As Represented By The Secretary Of The Navy Simplified fabrication method for high-performance FET
DE3232837A1 (de) * 1982-09-03 1984-03-08 Siemens AG, 1000 Berlin und 8000 München Verfahren zum herstellen einer 2-ebenen-metallisierung fuer halbleiterbauelemente, insbesondere fuer leistungshalbleiterbauelemente wie thyristoren
US4526859A (en) * 1983-12-12 1985-07-02 International Business Machines Corporation Metallization of a ceramic substrate
US4582722A (en) * 1984-10-30 1986-04-15 International Business Machines Corporation Diffusion isolation layer for maskless cladding process
US4663186A (en) * 1986-04-24 1987-05-05 International Business Machines Corporation Screenable paste for use as a barrier layer on a substrate during maskless cladding
JPH0238571A (ja) * 1988-07-27 1990-02-07 Tokyo Electron Ltd 処理装置
US5226232A (en) * 1990-05-18 1993-07-13 Hewlett-Packard Company Method for forming a conductive pattern on an integrated circuit
US5203944A (en) * 1991-10-10 1993-04-20 Prinz Fritz B Method for fabrication of three-dimensional articles by thermal spray deposition using masks as support structures
US6713237B2 (en) 2000-07-27 2004-03-30 Seagate Technology Llc Single layer lift-off method for making an electronic device
JP3867017B2 (ja) * 2002-05-24 2007-01-10 Ｔｄｋ株式会社 パターン形成方法、マイクロデバイスの製造方法、薄膜磁気ヘッドの製造方法、磁気ヘッドスライダの製造方法、磁気ヘッド装置の製造方法、磁気記録再生装置の製造方法
JP2007517410A (ja) * 2003-12-30 2007-06-28 スリーエム イノベイティブ プロパティズ カンパニー パターン回路およびその製造方法
US9219178B2 (en) * 2014-03-21 2015-12-22 Kabushiki Kaisha Toshiba Method to fabricate collimator structures on a direct conversion semiconductor X-ray detector

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2192382A1 (fr) * 1972-07-13 1974-02-08 Intersil Inc
FR2216369A1 (fr) * 1973-01-31 1974-08-30 Siemens Ag

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US2728693A (en) * 1953-08-24 1955-12-27 Motorola Inc Method of forming electrical conductor upon an insulating base
US3192136A (en) * 1962-09-14 1965-06-29 Sperry Rand Corp Method of preparing precision screens
US3700445A (en) * 1971-07-29 1972-10-24 Us Navy Photoresist processing method for fabricating etched microcircuits
JPS51414B2 (fr) * 1971-11-19 1976-01-08
US3837907A (en) * 1972-03-22 1974-09-24 Bell Telephone Labor Inc Multiple-level metallization for integrated circuits
JPS4937541A (fr) * 1972-08-09 1974-04-08

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2192382A1 (fr) * 1972-07-13 1974-02-08 Intersil Inc
FR2216369A1 (fr) * 1973-01-31 1974-08-30 Siemens Ag

Also Published As

Publication number Publication date
IT1056759B (it) 1982-02-20
GB1522004A (en) 1978-08-23
DE2555299A1 (de) 1976-09-16
JPS5816548B2 (ja) 1983-03-31
CA1071761A (fr) 1980-02-12
JPS51135333A (en) 1976-11-24
FR2303379B1 (fr) 1978-05-19
US3957552A (en) 1976-05-18

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Legal Events

Date Code Title Description
ST Notification of lapse