FR2371692A1 - Procede permettant d'injecter des charges dans des dispositifs a effet de champ et structure de test en resultant - Google Patents

Procede permettant d'injecter des charges dans des dispositifs a effet de champ et structure de test en resultant

Info

Publication number
FR2371692A1
FR2371692A1 FR7731530A FR7731530A FR2371692A1 FR 2371692 A1 FR2371692 A1 FR 2371692A1 FR 7731530 A FR7731530 A FR 7731530A FR 7731530 A FR7731530 A FR 7731530A FR 2371692 A1 FR2371692 A1 FR 2371692A1
Authority
FR
France
Prior art keywords
substrate
source
drain electrodes
test structure
bias
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
FR7731530A
Other languages
English (en)
Other versions
FR2371692B1 (fr
Inventor
Lowell F Howard
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Publication of FR2371692A1 publication Critical patent/FR2371692A1/fr
Application granted granted Critical
Publication of FR2371692B1 publication Critical patent/FR2371692B1/fr
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0466—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells with charge storage in an insulating layer, e.g. metal-nitride-oxide-silicon [MNOS], silicon-oxide-nitride-oxide-silicon [SONOS]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/69—IGFETs having charge trapping gate insulators, e.g. MNOS transistors

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Non-Volatile Memory (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)
  • Testing Of Individual Semiconductor Devices (AREA)

Abstract

Structure de test pour évaluer les effets de la variation de la tension de seuil, générée par des fuites, caractérisée en ce qu'elle comprend : un transistor à effet de champ à porte isolée, composé d'électrodes de source et de drain 12, 14, d'une électrode de porte commandant une région de canal 18 et d'un substrat 10, des moyens (Vg, Vsub )1 pour appliquer un potentiel fixe entre ladite électrode et ledit substrat, ledit potentiel fixe étant d'une grandeur et d'une polarité telles qu'il provoque la formation d'une région d'appauvrissement dans ladite région de canal; et des moyens de couplage desdites électrodes de source et de drain à une source d'impulsions bipolaires (Vp) afin de polariser lesdites électrodes de source et de drain dans des conditions de polarisation en direct et en inverse, séquentiellement alternées par rapport au potentiel dudit substrat, afin d'injecter des porteurs minoritaires dans le substrat dudit transistor pendant ladite polarisation en direct, ces porteurs étant ensuite injectés dans la porte isolée dudit transistor pendant ladite polarisation en inverse. Application à la fabrication des dispositifs intégrés à semi-conducteur.
FR7731530A 1976-11-19 1977-10-07 Procede permettant d'injecter des charges dans des dispositifs a effet de champ et structure de test en resultant Granted FR2371692A1 (fr)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US05/743,253 US4075653A (en) 1976-11-19 1976-11-19 Method for injecting charge in field effect devices

Publications (2)

Publication Number Publication Date
FR2371692A1 true FR2371692A1 (fr) 1978-06-16
FR2371692B1 FR2371692B1 (fr) 1982-04-09

Family

ID=24988084

Family Applications (1)

Application Number Title Priority Date Filing Date
FR7731530A Granted FR2371692A1 (fr) 1976-11-19 1977-10-07 Procede permettant d'injecter des charges dans des dispositifs a effet de champ et structure de test en resultant

Country Status (5)

Country Link
US (1) US4075653A (fr)
JP (1) JPS5364482A (fr)
DE (1) DE2749711A1 (fr)
FR (1) FR2371692A1 (fr)
GB (1) GB1535019A (fr)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58100459A (ja) * 1981-12-10 1983-06-15 Nippon Telegr & Teleph Corp <Ntt> Ｍｏｓ型半導体装置の特性安定化処理方法
JPS6117836A (ja) * 1984-07-04 1986-01-25 Matsushita Electric Ind Co Ltd 電気コンロ
US5289030A (en) 1991-03-06 1994-02-22 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device with oxide layer
JP2794678B2 (ja) * 1991-08-26 1998-09-10 株式会社 半導体エネルギー研究所 絶縁ゲイト型半導体装置およびその作製方法
US6624450B1 (en) 1992-03-27 2003-09-23 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and method for forming the same
US5598009A (en) * 1994-11-15 1997-01-28 Advanced Micro Devices, Inc. Hot carrier injection test structure and testing technique for statistical evaluation
DE10224956A1 (de) * 2002-06-05 2004-01-08 Infineon Technologies Ag Verfahren zur Einstellung der Einsatzspannung eines Feldeffekttansistors, Feldeffekttransistor sowie integrierte Schaltung
JP4967476B2 (ja) * 2005-07-04 2012-07-04 株式会社デンソー 半導体装置の検査方法
WO2023012893A1 (fr) * 2021-08-03 2023-02-09 ユニサンティス エレクトロニクス シンガポール プライベート リミテッド Dispositif de mémoire utilisant un élément semi-conducteur
CN115792445B (zh) * 2022-11-25 2026-04-14 南京信息工程大学 一种电介质中载流子注入势垒的测试提取方法

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3646527A (en) * 1969-04-12 1972-02-29 Nippon Electric Co Electronic memory circuit employing semiconductor memory elements and a method for writing to the memory element

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
NL7208026A (fr) * 1972-06-13 1973-12-17

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3646527A (en) * 1969-04-12 1972-02-29 Nippon Electric Co Electronic memory circuit employing semiconductor memory elements and a method for writing to the memory element

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
EXBK/71 *

Also Published As

Publication number Publication date
US4075653A (en) 1978-02-21
FR2371692B1 (fr) 1982-04-09
JPS5364482A (en) 1978-06-08
GB1535019A (en) 1978-12-06
DE2749711A1 (de) 1978-05-24
JPS5548459B2 (fr) 1980-12-05

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Legal Events

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