FR2380636A1 - Procede pour former une couche electriquement isolante sur un substrat - Google Patents

Procede pour former une couche electriquement isolante sur un substrat

Info

Publication number
FR2380636A1
FR2380636A1 FR7803999A FR7803999A FR2380636A1 FR 2380636 A1 FR2380636 A1 FR 2380636A1 FR 7803999 A FR7803999 A FR 7803999A FR 7803999 A FR7803999 A FR 7803999A FR 2380636 A1 FR2380636 A1 FR 2380636A1
Authority
FR
France
Prior art keywords
insulating layer
substrate
forming
electrically insulating
metallic configuration
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
FR7803999A
Other languages
English (en)
Other versions
FR2380636B1 (fr
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Koninklijke Philips NV
Original Assignee
Philips Gloeilampenfabrieken NV
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Philips Gloeilampenfabrieken NV filed Critical Philips Gloeilampenfabrieken NV
Publication of FR2380636A1 publication Critical patent/FR2380636A1/fr
Application granted granted Critical
Publication of FR2380636B1 publication Critical patent/FR2380636B1/fr
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01F—MAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
    • H01F41/00—Apparatus or processes specially adapted for manufacturing or assembling magnets, inductances or transformers; Apparatus or processes specially adapted for manufacturing materials characterised by their magnetic properties
    • H01F41/32—Apparatus or processes specially adapted for manufacturing or assembling magnets, inductances or transformers; Apparatus or processes specially adapted for manufacturing materials characterised by their magnetic properties for applying conductive, insulating or magnetic material on a magnetic film, specially adapted for a thin magnetic film
    • H01F41/34—Apparatus or processes specially adapted for manufacturing or assembling magnets, inductances or transformers; Apparatus or processes specially adapted for manufacturing materials characterised by their magnetic properties for applying conductive, insulating or magnetic material on a magnetic film, specially adapted for a thin magnetic film in patterns, e.g. by lithography
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
    • G11B5/00—Recording by magnetisation or demagnetisation of a record carrier; Reproducing by magnetic means; Record carriers therefor
    • G11B5/127—Structure or manufacture of heads, e.g. inductive
    • G11B5/31—Structure or manufacture of heads, e.g. inductive using thin films
    • G11B5/3163—Fabrication methods or processes specially adapted for a particular head structure, e.g. using base layers for electroplating, using functional layers for masking, using energy or particle beams for shaping the structure or modifying the properties of the basic layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/20—Dry etching; Plasma etching; Reactive-ion etching
    • H10P50/26—Dry etching; Plasma etching; Reactive-ion etching of conductive or resistive materials
    • H10P50/262—Dry etching; Plasma etching; Reactive-ion etching of conductive or resistive materials by physical means only
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/20—Dry etching; Plasma etching; Reactive-ion etching
    • H10P50/28—Dry etching; Plasma etching; Reactive-ion etching of insulating materials
    • H10P50/282—Dry etching; Plasma etching; Reactive-ion etching of insulating materials of inorganic materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/074—Manufacture or treatment of dielectric parts thereof of dielectric parts comprising thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H10W20/077—Manufacture or treatment of dielectric parts thereof of dielectric parts comprising thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers on sidewalls or on top surfaces of conductors

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Power Engineering (AREA)
  • Magnetic Heads (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

Procédé pour former des chanfreins à une configuration métallique pour préparer celle-ci à son recouvrement par une couche isolante. Le dépôt proprement dit de la couche isolante sur la configuration métallique formée par voie galvanique sur un substrat est dans ce cas précédé d'un décapage pulvérisation sous l'action duquel les bords arrondis de la configuration métallique deviennent des chanfreins, c'est-à-dire des bords qui sont obliques par rapport à la surface de substrat. Application à la fabrication de têtes magnétiques réalisées en minces couches.
FR7803999A 1977-02-15 1978-02-13 Procede pour former une couche electriquement isolante sur un substrat Expired FR2380636B1 (fr)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
NL7701559A NL7701559A (nl) 1977-02-15 1977-02-15 Het maken van schuine hellingen aan metaal- patronen, alsmede substraat voor een geinte- greerde schakeling voorzien van een dergelijk patroon.

Publications (2)

Publication Number Publication Date
FR2380636A1 true FR2380636A1 (fr) 1978-09-08
FR2380636B1 FR2380636B1 (fr) 1985-06-14

Family

ID=19827979

Family Applications (1)

Application Number Title Priority Date Filing Date
FR7803999A Expired FR2380636B1 (fr) 1977-02-15 1978-02-13 Procede pour former une couche electriquement isolante sur un substrat

Country Status (8)

Country Link
US (1) US4176016A (fr)
JP (1) JPS53100785A (fr)
CA (1) CA1102922A (fr)
DE (1) DE2804602C2 (fr)
FR (1) FR2380636B1 (fr)
GB (1) GB1553181A (fr)
HK (1) HK8880A (fr)
NL (1) NL7701559A (fr)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2495333A1 (fr) * 1980-08-30 1982-06-04 Philips Nv Procede de realisation d'un capteur de champ magnetique sous forme d'une couche mince
FR2619457A1 (fr) * 1987-08-14 1989-02-17 Commissariat Energie Atomique Procede d'obtention d'un motif notamment en materiau ferromagnetique ayant des flancs de pente differente et tete magnetique comportant un tel motif

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5759355A (en) * 1980-09-26 1982-04-09 Fujitsu Ltd Manufacture of semiconductor device
JPH0697660B2 (ja) * 1985-03-23 1994-11-30 日本電信電話株式会社 薄膜形成方法
DE4400032C1 (de) * 1994-01-03 1995-08-31 Gold Star Electronics Halbleitereinrichtung und Verfahren zu deren Herstellung
US5756397A (en) * 1993-12-28 1998-05-26 Lg Semicon Co., Ltd. Method of fabricating a wiring in a semiconductor device
JP2016219452A (ja) * 2015-05-14 2016-12-22 富士通株式会社 多層基板及び多層基板の製造方法
CN114080088B (zh) * 2020-08-10 2024-05-31 鹏鼎控股(深圳)股份有限公司 电路板及其制备方法

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE2047799A1 (de) * 1969-10-31 1971-05-06 Fairchild Camera Instr Co Halbleiterbauelement
DE2123630A1 (en) * 1970-05-12 1971-12-02 Texas Instruments Inc Semiconductor with multilayer interconnections - using - successive masking and photo etching
US3700508A (en) * 1970-06-25 1972-10-24 Gen Instrument Corp Fabrication of integrated microcircuit devices
DE2307814A1 (de) * 1972-02-18 1973-08-30 Hitachi Ltd Verfahren zur herstellung elektrischer verbindungen
US3868723A (en) * 1973-06-29 1975-02-25 Ibm Integrated circuit structure accommodating via holes
US3983022A (en) * 1970-12-31 1976-09-28 International Business Machines Corporation Process for planarizing a surface

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3666548A (en) * 1970-01-06 1972-05-30 Ibm Monocrystalline semiconductor body having dielectrically isolated regions and method of forming
US3755123A (en) * 1971-03-30 1973-08-28 Method for sputtering a film on an irregular surface
US3804738A (en) * 1973-06-29 1974-04-16 Ibm Partial planarization of electrically insulative films by resputtering
US3839111A (en) * 1973-08-20 1974-10-01 Rca Corp Method of etching silicon oxide to produce a tapered edge thereon
US4022930A (en) * 1975-05-30 1977-05-10 Bell Telephone Laboratories, Incorporated Multilevel metallization for integrated circuits

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE2047799A1 (de) * 1969-10-31 1971-05-06 Fairchild Camera Instr Co Halbleiterbauelement
DE2123630A1 (en) * 1970-05-12 1971-12-02 Texas Instruments Inc Semiconductor with multilayer interconnections - using - successive masking and photo etching
US3700508A (en) * 1970-06-25 1972-10-24 Gen Instrument Corp Fabrication of integrated microcircuit devices
US3983022A (en) * 1970-12-31 1976-09-28 International Business Machines Corporation Process for planarizing a surface
DE2307814A1 (de) * 1972-02-18 1973-08-30 Hitachi Ltd Verfahren zur herstellung elektrischer verbindungen
US3868723A (en) * 1973-06-29 1975-02-25 Ibm Integrated circuit structure accommodating via holes

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2495333A1 (fr) * 1980-08-30 1982-06-04 Philips Nv Procede de realisation d'un capteur de champ magnetique sous forme d'une couche mince
FR2619457A1 (fr) * 1987-08-14 1989-02-17 Commissariat Energie Atomique Procede d'obtention d'un motif notamment en materiau ferromagnetique ayant des flancs de pente differente et tete magnetique comportant un tel motif
EP0304373A3 (en) * 1987-08-14 1989-03-08 Commissariat A L'energie Atomique Etablissement De Caractere Scientifique Technique Et Industriel Process for the obtention of a pattern, especially from a ferromagnetic material having flanks with different steepnesses, and magnetic head with such a pattern
US4944831A (en) * 1987-08-14 1990-07-31 Commissariat A L'energie Atomique Process for obtaining a pattern, in ferromagnetic material having differently sloping sides

Also Published As

Publication number Publication date
US4176016A (en) 1979-11-27
CA1102922A (fr) 1981-06-09
JPS53100785A (en) 1978-09-02
HK8880A (en) 1980-03-14
DE2804602C2 (de) 1985-01-17
JPS638613B2 (fr) 1988-02-23
FR2380636B1 (fr) 1985-06-14
DE2804602A1 (de) 1978-08-17
GB1553181A (en) 1979-09-19
NL7701559A (nl) 1978-08-17

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Legal Events

Date Code Title Description
ST Notification of lapse