FR2420168A1 - Dispositif de pre-traitement d'instructions dans un systeme de traitement de donnees - Google Patents

Dispositif de pre-traitement d'instructions dans un systeme de traitement de donnees

Info

Publication number
FR2420168A1
FR2420168A1 FR7902412A FR7902412A FR2420168A1 FR 2420168 A1 FR2420168 A1 FR 2420168A1 FR 7902412 A FR7902412 A FR 7902412A FR 7902412 A FR7902412 A FR 7902412A FR 2420168 A1 FR2420168 A1 FR 2420168A1
Authority
FR
France
Prior art keywords
instruction
fields
instructions
data processing
processing device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
FR7902412A
Other languages
English (en)
Other versions
FR2420168B1 (fr
Inventor
John S Liptay
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Publication of FR2420168A1 publication Critical patent/FR2420168A1/fr
Application granted granted Critical
Publication of FR2420168B1 publication Critical patent/FR2420168B1/fr
Expired legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/3004—Arrangements for executing specific machine instructions to perform operations on memory
    • G06F9/30043—LOAD or STORE instructions; Clear instruction
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3818—Decoding for concurrent execution
    • G06F9/3822—Parallel decoding, e.g. parallel decode units
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3838—Dependency mechanisms, e.g. register scoreboarding
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3867—Concurrent instruction execution, e.g. pipeline or look ahead using instruction pipelines

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Advance Control (AREA)

Abstract

Circuit logique permettant le pré-décodage et la mise en file d'attente d'instructions. Les circuits peuvent être commandés par des instructions de chargement de registres indentifiant un, deux ou plusieurs registres généraux. Deux champs d'identification de registres sont prévus pour chaque instruction pré-décodée introduite dans une file d'instructions. Des circuits de comparaison comparent ces champs et les champs d'adressage de registres dans l'instruction en cours de décodage. L'invention permet d'améliorer les performances des dispositifs de pré-décodage d'instructions.
FR7902412A 1978-03-16 1979-01-25 Dispositif de pre-traitement d'instructions dans un systeme de traitement de donnees Expired FR2420168B1 (fr)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US88709378A 1978-03-16 1978-03-16

Publications (2)

Publication Number Publication Date
FR2420168A1 true FR2420168A1 (fr) 1979-10-12
FR2420168B1 FR2420168B1 (fr) 1986-09-26

Family

ID=25390443

Family Applications (1)

Application Number Title Priority Date Filing Date
FR7902412A Expired FR2420168B1 (fr) 1978-03-16 1979-01-25 Dispositif de pre-traitement d'instructions dans un systeme de traitement de donnees

Country Status (5)

Country Link
JP (1) JPS54127649A (fr)
DE (1) DE2906685A1 (fr)
FR (1) FR2420168B1 (fr)
GB (1) GB2016753A (fr)
IT (1) IT1166667B (fr)

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2561429B1 (fr) * 1984-03-13 1986-09-19 Trt Telecom Radio Electr Dispositif d'adressage pour fournir a une memoire des codes d'adresse
FI86484C (fi) * 1984-04-27 1992-08-25 Honeywell Inf Systems Styrorgan i en digital datamaskin.
DE3650578T2 (de) * 1985-06-17 1997-03-06 Nippon Electric Co Informationsverarbeitungssystem mit einer Steuerschaltung zum Abwarten einer Registererneuerung und einem Aufnahmemittel des zu erneuernden Registers
JPS6227829A (ja) * 1985-07-30 1987-02-05 Fujitsu Ltd 多重ロード命令制御装置
US5167026A (en) * 1989-02-03 1992-11-24 Digital Equipment Corporation Simultaneously or sequentially decoding multiple specifiers of a variable length pipeline instruction based on detection of modified value of specifier registers
US5142631A (en) * 1989-02-03 1992-08-25 Digital Equipment Corporation System for queuing individual read or write mask and generating respective composite mask for controlling access to general purpose register
US5432918A (en) * 1990-06-29 1995-07-11 Digital Equipment Corporation Method and apparatus for ordering read and write operations using conflict bits in a write queue
DE69130138T2 (de) * 1990-06-29 1999-05-06 Digital Equipment Corp., Maynard, Mass. Sprungvorhersageeinheit für hochleistungsfähigen Prozessor
US5471591A (en) * 1990-06-29 1995-11-28 Digital Equipment Corporation Combined write-operand queue and read-after-write dependency scoreboard
US5450555A (en) * 1990-06-29 1995-09-12 Digital Equipment Corporation Register logging in pipelined computer using register log queue of register content changes and base queue of register log queue pointers for respective instructions
US11457671B2 (en) 2019-12-20 2022-10-04 Maddox Holdings Inc. Maternity undergarment for gentle support and shape enhancement

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3477063A (en) * 1967-10-26 1969-11-04 Ibm Controller for data processing system

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5320180B2 (fr) * 1972-05-09 1978-06-24
JPS5240946B2 (fr) * 1972-09-06 1977-10-15
JPS5041442A (fr) * 1973-08-16 1975-04-15
JPS5318931A (en) * 1976-08-06 1978-02-21 Hitachi Ltd Information processor

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3477063A (en) * 1967-10-26 1969-11-04 Ibm Controller for data processing system

Also Published As

Publication number Publication date
JPS6112289B2 (fr) 1986-04-07
JPS54127649A (en) 1979-10-03
DE2906685A1 (de) 1979-09-20
FR2420168B1 (fr) 1986-09-26
GB2016753A (en) 1979-09-26
IT7920567A0 (it) 1979-02-27
DE2906685C2 (fr) 1988-04-14
GB2016753B (fr)
IT1166667B (it) 1987-05-06

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Legal Events

Date Code Title Description
ST Notification of lapse