FR2425113A1 - Multiple coupler for active computers including one master - uses bidirectional programmable input-output gate circuits - Google Patents

Multiple coupler for active computers including one master - uses bidirectional programmable input-output gate circuits

Info

Publication number
FR2425113A1
FR2425113A1 FR7910826A FR7910826A FR2425113A1 FR 2425113 A1 FR2425113 A1 FR 2425113A1 FR 7910826 A FR7910826 A FR 7910826A FR 7910826 A FR7910826 A FR 7910826A FR 2425113 A1 FR2425113 A1 FR 2425113A1
Authority
FR
France
Prior art keywords
master
output gate
gate circuits
programmable input
computers including
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
FR7910826A
Other languages
French (fr)
Inventor
Wolfgang Henzler
Karl Herrmann
Eberhard Kehrer
Eberhard Krug
Wolfgang Schone
Gunter Wollenberg
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NUMERIK KARL MARX VEB
Original Assignee
NUMERIK KARL MARX VEB
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NUMERIK KARL MARX VEB filed Critical NUMERIK KARL MARX VEB
Publication of FR2425113A1 publication Critical patent/FR2425113A1/en
Withdrawn legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G06F15/163—Interprocessor communication
    • G06F15/17—Interprocessor communication using an input/output type connection, e.g. channel, I/O port
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Software Systems (AREA)
  • Multi Processors (AREA)
  • Pharmaceuticals Containing Other Organic And Inorganic Compounds (AREA)
  • Exchange Systems With Centralized Control (AREA)

Abstract

A coupling for several active computing devices, one of which is a master and the rest slave units, involves couplers, address, control, and data highways combined to enable a synchronous data exchange using an interrupt method. It is of the simplest possible construction, low circuit complexity and high efficiency and makes extensive use of standardised component groups. Bidirectional programmable input/output gate circuits for each computer contain data, address, and control sections and are interconnected via highways. Special control circuits prevent accessing conflicts.
FR7910826A 1978-05-03 1979-04-27 Multiple coupler for active computers including one master - uses bidirectional programmable input-output gate circuits Withdrawn FR2425113A1 (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
DD20514178A DD142135A3 (en) 1978-05-03 1978-05-03 MORE COMPUTER COUPLING

Publications (1)

Publication Number Publication Date
FR2425113A1 true FR2425113A1 (en) 1979-11-30

Family

ID=5512467

Family Applications (1)

Application Number Title Priority Date Filing Date
FR7910826A Withdrawn FR2425113A1 (en) 1978-05-03 1979-04-27 Multiple coupler for active computers including one master - uses bidirectional programmable input-output gate circuits

Country Status (6)

Country Link
BG (1) BG34874A1 (en)
CS (1) CS272256B1 (en)
DD (1) DD142135A3 (en)
DE (1) DE2912734C2 (en)
FR (1) FR2425113A1 (en)
SU (1) SU1337902A1 (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0044033A1 (en) * 1980-07-11 1982-01-20 Siemens Aktiengesellschaft Device for the fast transfer of data blocks between two operational processors
EP0171856A1 (en) * 1984-08-14 1986-02-19 Telecommunications Radioelectriques Et Telephoniques T.R.T. Signal processor and hierarchical multiprocessing structure comprising at least one such processor
EP0142329A3 (en) * 1983-11-08 1986-04-02 Kabushiki Kaisha Ishida Koki Seisakusho Control system for combinatorial weighing or counting apparatus

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB9008362D0 (en) * 1990-04-12 1990-06-13 Hackremco No 574 Limited Banking computer system
EP0918413B1 (en) * 1996-12-16 2004-02-25 Samsung Electronics Co., Ltd. Method for sending e-mail messages in a local area network, and device for applying same
KR100383642B1 (en) * 1996-12-16 2003-06-18 삼성전자주식회사 Method of transmitting message between subscriber units formed in network
RU2139566C1 (en) * 1997-09-04 1999-10-10 Экспериментальное научно-производственное объединение "Специализированные электронные системы" Multiprocessor data processing system
RU2210104C2 (en) * 2001-06-28 2003-08-10 Езерский Сергей Владимирович Multiprocessor information-management relay protection and automatic control system

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3634830A (en) * 1969-06-13 1972-01-11 Ibm Modular computer sharing system with intercomputer communication control apparatus
GB1279955A (en) * 1971-04-15 1972-06-28 Standard Telephones Cables Ltd Improvements in or relating to computer systems
DE2446970A1 (en) * 1973-10-12 1975-04-17 Burroughs Corp DATA PROCESSING SYSTEM WITH INTERFACE UNIT BETWEEN COMPUTERS AND EDGE UNITS
US3972023A (en) * 1974-12-30 1976-07-27 International Business Machines Corporation I/O data transfer control system
FR2328248A1 (en) * 1975-10-14 1977-05-13 Texas Instruments Inc OMNIBUS TRANSMISSION LINES COUPLING DEVICE, ESPECIALLY FOR COMMUNICATION BETWEEN MULTIPROCESSORS

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3634830A (en) * 1969-06-13 1972-01-11 Ibm Modular computer sharing system with intercomputer communication control apparatus
GB1279955A (en) * 1971-04-15 1972-06-28 Standard Telephones Cables Ltd Improvements in or relating to computer systems
DE2446970A1 (en) * 1973-10-12 1975-04-17 Burroughs Corp DATA PROCESSING SYSTEM WITH INTERFACE UNIT BETWEEN COMPUTERS AND EDGE UNITS
US3972023A (en) * 1974-12-30 1976-07-27 International Business Machines Corporation I/O data transfer control system
FR2328248A1 (en) * 1975-10-14 1977-05-13 Texas Instruments Inc OMNIBUS TRANSMISSION LINES COUPLING DEVICE, ESPECIALLY FOR COMMUNICATION BETWEEN MULTIPROCESSORS

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
EXBK/75 *

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0044033A1 (en) * 1980-07-11 1982-01-20 Siemens Aktiengesellschaft Device for the fast transfer of data blocks between two operational processors
EP0142329A3 (en) * 1983-11-08 1986-04-02 Kabushiki Kaisha Ishida Koki Seisakusho Control system for combinatorial weighing or counting apparatus
US4658919A (en) * 1983-11-08 1987-04-21 Kabushiki Kaisha Ishida Koki Seisakusho Control system for combinatorial weighing or counting apparatus
EP0171856A1 (en) * 1984-08-14 1986-02-19 Telecommunications Radioelectriques Et Telephoniques T.R.T. Signal processor and hierarchical multiprocessing structure comprising at least one such processor
FR2569290A1 (en) * 1984-08-14 1986-02-21 Trt Telecom Radio Electr PROCESSOR FOR SIGNAL PROCESSING AND HIERARCHISED MULTIFRAITE STRUCTURE COMPRISING AT LEAST ONE SUCH PROCESSOR

Also Published As

Publication number Publication date
BG34874A1 (en) 1983-12-15
SU1337902A1 (en) 1987-09-15
DD142135A3 (en) 1980-06-11
DE2912734C2 (en) 1985-01-17
DE2912734A1 (en) 1979-11-15
CS272256B1 (en) 1991-01-15

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Legal Events

Date Code Title Description
ST Notification of lapse