FR2432247A1 - Dispositif pour transformer un signal logique a deux niveaux en un signal a deux autres niveaux - Google Patents

Dispositif pour transformer un signal logique a deux niveaux en un signal a deux autres niveaux

Info

Publication number
FR2432247A1
FR2432247A1 FR7821989A FR7821989A FR2432247A1 FR 2432247 A1 FR2432247 A1 FR 2432247A1 FR 7821989 A FR7821989 A FR 7821989A FR 7821989 A FR7821989 A FR 7821989A FR 2432247 A1 FR2432247 A1 FR 2432247A1
Authority
FR
France
Prior art keywords
circuit
processing circuits
level shift
transistor
voltage level
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
FR7821989A
Other languages
English (en)
Other versions
FR2432247B1 (fr
Inventor
Henri Badoual
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Telecommunications Radioelectriques et Telephoniques SA TRT
Original Assignee
Telecommunications Radioelectriques et Telephoniques SA TRT
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Telecommunications Radioelectriques et Telephoniques SA TRT filed Critical Telecommunications Radioelectriques et Telephoniques SA TRT
Priority to FR7821989A priority Critical patent/FR2432247A1/fr
Publication of FR2432247A1 publication Critical patent/FR2432247A1/fr
Application granted granted Critical
Publication of FR2432247B1 publication Critical patent/FR2432247B1/fr
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements
    • H03K19/018—Coupling arrangements; Interface arrangements using bipolar transistors only
    • H03K19/01806—Interface arrangements
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/01—Shaping pulses
    • H03K5/08—Shaping pulses by limiting; by thresholding; by slicing, i.e. combined limiting and thresholding

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Nonlinear Science (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Logic Circuits (AREA)

Abstract

Ce dispositif est remarquable en ce qu'il est constitué, d'une part, par un circuit de changement d'écart de tension dont l'entrée reçoit le signal logique d'entrée et, d'autre part, par un circuit de déplacement de niveau dont l'entrée est reliée à la sortie du circuit de changement d'écart de tension et à la sortie duquel apparaissent les signaux logiques de sortie. Application : Interface de circuits de logiques différentes.
FR7821989A 1978-07-25 1978-07-25 Dispositif pour transformer un signal logique a deux niveaux en un signal a deux autres niveaux Granted FR2432247A1 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
FR7821989A FR2432247A1 (fr) 1978-07-25 1978-07-25 Dispositif pour transformer un signal logique a deux niveaux en un signal a deux autres niveaux

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR7821989A FR2432247A1 (fr) 1978-07-25 1978-07-25 Dispositif pour transformer un signal logique a deux niveaux en un signal a deux autres niveaux

Publications (2)

Publication Number Publication Date
FR2432247A1 true FR2432247A1 (fr) 1980-02-22
FR2432247B1 FR2432247B1 (fr) 1981-01-02

Family

ID=9211146

Family Applications (1)

Application Number Title Priority Date Filing Date
FR7821989A Granted FR2432247A1 (fr) 1978-07-25 1978-07-25 Dispositif pour transformer un signal logique a deux niveaux en un signal a deux autres niveaux

Country Status (1)

Country Link
FR (1) FR2432247A1 (fr)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1988003726A1 (fr) * 1986-11-07 1988-05-19 Emco Display Technology Limited Ameliorations apportees au traitement de signaux

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3529179A (en) * 1967-11-01 1970-09-15 Us Army Logic noise suppressor
US3648064A (en) * 1968-07-01 1972-03-07 Nippon Telegraph & Telephone Multiple signal level high-speed logic circuit device

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3529179A (en) * 1967-11-01 1970-09-15 Us Army Logic noise suppressor
US3648064A (en) * 1968-07-01 1972-03-07 Nippon Telegraph & Telephone Multiple signal level high-speed logic circuit device

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
NV700/76 *

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1988003726A1 (fr) * 1986-11-07 1988-05-19 Emco Display Technology Limited Ameliorations apportees au traitement de signaux

Also Published As

Publication number Publication date
FR2432247B1 (fr) 1981-01-02

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Legal Events

Date Code Title Description
DR Decision of the appeal court due to an appeal at law against decisions of the director of the inpi, except decision of lapse
ST Notification of lapse