FR2440032A1 - Methode de detection de defauts dans un systeme de traitement de donnees a multiprocesseur - Google Patents

Methode de detection de defauts dans un systeme de traitement de donnees a multiprocesseur

Info

Publication number
FR2440032A1
FR2440032A1 FR7830292A FR7830292A FR2440032A1 FR 2440032 A1 FR2440032 A1 FR 2440032A1 FR 7830292 A FR7830292 A FR 7830292A FR 7830292 A FR7830292 A FR 7830292A FR 2440032 A1 FR2440032 A1 FR 2440032A1
Authority
FR
France
Prior art keywords
processor
control
memory
checked
monitoring
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
FR7830292A
Other languages
English (en)
Inventor
Frederick Henry Rees
Martin Geoffrey Cope
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
STC PLC
Original Assignee
Standard Telephone and Cables PLC
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Standard Telephone and Cables PLC filed Critical Standard Telephone and Cables PLC
Priority to FR7830292A priority Critical patent/FR2440032A1/fr
Publication of FR2440032A1 publication Critical patent/FR2440032A1/fr
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04Q—SELECTING
    • H04Q3/00—Selecting arrangements
    • H04Q3/42—Circuit arrangements for indirect selecting controlled by common circuits, e.g. register controller, marker
    • H04Q3/54—Circuit arrangements for indirect selecting controlled by common circuits, e.g. register controller, marker in which the logic circuitry controlling the exchange is centralised
    • H04Q3/545—Circuit arrangements for indirect selecting controlled by common circuits, e.g. register controller, marker in which the logic circuitry controlling the exchange is centralised using a stored program
    • H04Q3/54541—Circuit arrangements for indirect selecting controlled by common circuits, e.g. register controller, marker in which the logic circuitry controlling the exchange is centralised using a stored program using multi-processor systems
    • H04Q3/5455—Multi-processor, parallelism, distributed systems
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
    • G06F11/0706—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment
    • G06F11/0721—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment within a central processing unit [CPU]
    • G06F11/0724—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment within a central processing unit [CPU] in a multiprocessor or a multi-core unit
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
    • G06F11/0751—Error or fault detection not based on redundancy
    • G06F11/0763—Error or fault detection not based on redundancy by bit configuration check, e.g. of formats or tags
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/16—Error detection or correction of the data by redundancy in hardware
    • G06F11/20—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements
    • G06F11/202—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements where processing functionality is redundant
    • G06F11/2023—Failover techniques
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/16—Error detection or correction of the data by redundancy in hardware
    • G06F11/20—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements
    • G06F11/202—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements where processing functionality is redundant
    • G06F11/2035—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements where processing functionality is redundant without idle spare hardware

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Quality & Reliability (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Debugging And Monitoring (AREA)

Abstract

DANS UN SYSTEME A MULTIPROCESSEUR COMPRENANT UN PROCESSEUR CENTRAL QUI CONFIE DES TACHES DE TRAITEMENT DE DONNEES A UN CERTAIN NOMBRE DE PROCESSEURS SATELLITES, L'INVENTION CONCERNE LA TECHNIQUE ET LES MOYENS MIS EN OEUVRE PAR LE PROCESSEUR CENTRAL POUR DETECTER LES DEFAUTS DE FONCTIONNEMENT DES PROCESSEURS SATELLITES. DURANT L'EXECUTION D'UNE TACHE, CHAQUE PROCESSEUR SATELLITE 1 ADDITIONNE DES MOTS DE COMMANDE EXTRAITS DE SA MEMOIRE DE PROGRAMME 2. IL S'AGIT DE MOTS DE DEUX OCTETS ET CHAQUE OCTET EST AJOUTE AU CONTENU D'UN REGISTRE PARTICULIER A HUIT BITS. LES RESULTATS SONT TRANSFERES DANS UNE MEMOIRE A ACCES SELECTIF 3 ACCESSIBLE A TOUS LES PROCESSEURS PAR L'INTERMEDIAIRE DE SELECTEURS 4. LE PROCESSEUR CENTRAL VERIFIE CYCLIQUEMENT LES RESULTATS FOURNIS PAR CHAQUE PROCESSEUR SATELLITE. APPLICATION PARTICULIERE AU SOUS-SYSTEME DE SIGNALISATION D'UN RESEAU DE TELECOMMUNICATIONS.
FR7830292A 1978-10-25 1978-10-25 Methode de detection de defauts dans un systeme de traitement de donnees a multiprocesseur Withdrawn FR2440032A1 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
FR7830292A FR2440032A1 (fr) 1978-10-25 1978-10-25 Methode de detection de defauts dans un systeme de traitement de donnees a multiprocesseur

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR7830292A FR2440032A1 (fr) 1978-10-25 1978-10-25 Methode de detection de defauts dans un systeme de traitement de donnees a multiprocesseur

Publications (1)

Publication Number Publication Date
FR2440032A1 true FR2440032A1 (fr) 1980-05-23

Family

ID=9214129

Family Applications (1)

Application Number Title Priority Date Filing Date
FR7830292A Withdrawn FR2440032A1 (fr) 1978-10-25 1978-10-25 Methode de detection de defauts dans un systeme de traitement de donnees a multiprocesseur

Country Status (1)

Country Link
FR (1) FR2440032A1 (fr)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2511802A1 (fr) * 1981-08-22 1983-02-25 Bosch Gmbh Robert Procede pour accroitre la fiabilite des memoires a semi-conducteurs dans les vehicules automobiles
EP0058948A3 (en) * 1981-02-25 1985-01-16 Nissan Motor Company, Limited Multiple computer system

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3745316A (en) * 1971-12-13 1973-07-10 Elliott Bros Computer checking system
US3996567A (en) * 1972-05-23 1976-12-07 Telefonaktiebolaget L M Ericsson Apparatus for indicating abnormal program execution in a process controlling computer operating in real time on different priority levels
FR2343379A1 (fr) * 1976-03-04 1977-09-30 Post Office Equipement de traitement des donnees

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3745316A (en) * 1971-12-13 1973-07-10 Elliott Bros Computer checking system
US3996567A (en) * 1972-05-23 1976-12-07 Telefonaktiebolaget L M Ericsson Apparatus for indicating abnormal program execution in a process controlling computer operating in real time on different priority levels
FR2343379A1 (fr) * 1976-03-04 1977-09-30 Post Office Equipement de traitement des donnees

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0058948A3 (en) * 1981-02-25 1985-01-16 Nissan Motor Company, Limited Multiple computer system
US4621322A (en) * 1981-02-25 1986-11-04 Nissan Motor Company, Limited CPU self-test system including the capability of disconnecting a faulty CPU from the common bus of a plural CPU system
FR2511802A1 (fr) * 1981-08-22 1983-02-25 Bosch Gmbh Robert Procede pour accroitre la fiabilite des memoires a semi-conducteurs dans les vehicules automobiles

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Legal Events

Date Code Title Description
ST Notification of lapse