FR2654881B1 - Reseau logique programmable en technologie cmos. - Google Patents

Reseau logique programmable en technologie cmos.

Info

Publication number
FR2654881B1
FR2654881B1 FR8915846A FR8915846A FR2654881B1 FR 2654881 B1 FR2654881 B1 FR 2654881B1 FR 8915846 A FR8915846 A FR 8915846A FR 8915846 A FR8915846 A FR 8915846A FR 2654881 B1 FR2654881 B1 FR 2654881B1
Authority
FR
France
Prior art keywords
programmable logic
cmos technology
logic network
network
cmos
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
FR8915846A
Other languages
English (en)
Other versions
FR2654881A1 (fr
Inventor
Philippe Chaisemartin
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
STMicroelectronics SA
STMicroelectronics lnc USA
Original Assignee
SGS Thomson Microelectronics SA
SGS Thomson Microelectronics Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by SGS Thomson Microelectronics SA, SGS Thomson Microelectronics Inc filed Critical SGS Thomson Microelectronics SA
Priority to FR8915846A priority Critical patent/FR2654881B1/fr
Publication of FR2654881A1 publication Critical patent/FR2654881A1/fr
Application granted granted Critical
Publication of FR2654881B1 publication Critical patent/FR2654881B1/fr
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/17704—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form the logic functions being realised by the interconnection of rows and columns
    • H03K19/17708—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form the logic functions being realised by the interconnection of rows and columns using an AND matrix followed by an OR matrix, i.e. programmable logic arrays
    • H03K19/17716—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form the logic functions being realised by the interconnection of rows and columns using an AND matrix followed by an OR matrix, i.e. programmable logic arrays with synchronous operation, i.e. using clock signals, e.g. of I/O or coupling register
    • H03K19/1772—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form the logic functions being realised by the interconnection of rows and columns using an AND matrix followed by an OR matrix, i.e. programmable logic arrays with synchronous operation, i.e. using clock signals, e.g. of I/O or coupling register with synchronous operation of at least one of the logical matrixes

Landscapes

  • Physics & Mathematics (AREA)
  • Mathematical Physics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Logic Circuits (AREA)
FR8915846A 1989-11-23 1989-11-23 Reseau logique programmable en technologie cmos. Expired - Fee Related FR2654881B1 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
FR8915846A FR2654881B1 (fr) 1989-11-23 1989-11-23 Reseau logique programmable en technologie cmos.

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR8915846A FR2654881B1 (fr) 1989-11-23 1989-11-23 Reseau logique programmable en technologie cmos.

Publications (2)

Publication Number Publication Date
FR2654881A1 FR2654881A1 (fr) 1991-05-24
FR2654881B1 true FR2654881B1 (fr) 1994-10-14

Family

ID=9388011

Family Applications (1)

Application Number Title Priority Date Filing Date
FR8915846A Expired - Fee Related FR2654881B1 (fr) 1989-11-23 1989-11-23 Reseau logique programmable en technologie cmos.

Country Status (1)

Country Link
FR (1) FR2654881B1 (fr)

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
IT1042852B (it) * 1974-09-30 1980-01-30 Siemens Ag Disposizione di circuiti logici integrata e programmabile
US4554467A (en) * 1983-06-22 1985-11-19 Motorola, Inc. CMOS Flip-flop
IT1199895B (it) * 1985-07-17 1989-01-05 Csselt Centro Studi Circuito base di logica sequenziale in tecnologia cmos operante mediante un unico segnale di sincronismo
IT1195119B (it) * 1986-08-04 1988-10-12 Cselt Centro Studi Lab Telecom Perfezionamenti alle schiere logi che programmabili dinamiche a struttura nor nor realizzate in tecnolo gia c mos
JPH0253318A (ja) * 1988-07-06 1990-02-22 Ncr Corp ノーリークｃｍｏｓラツチ

Also Published As

Publication number Publication date
FR2654881A1 (fr) 1991-05-24

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