FR2797523B1 - Procede d'inspection d'un substrat semiconducteur - Google Patents

Procede d'inspection d'un substrat semiconducteur

Info

Publication number
FR2797523B1
FR2797523B1 FR0009956A FR0009956A FR2797523B1 FR 2797523 B1 FR2797523 B1 FR 2797523B1 FR 0009956 A FR0009956 A FR 0009956A FR 0009956 A FR0009956 A FR 0009956A FR 2797523 B1 FR2797523 B1 FR 2797523B1
Authority
FR
France
Prior art keywords
inspecting
semiconductor substrate
semiconductor
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
FR0009956A
Other languages
English (en)
Other versions
FR2797523A1 (fr
Inventor
Hideki Naruoka
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Publication of FR2797523A1 publication Critical patent/FR2797523A1/fr
Application granted granted Critical
Publication of FR2797523B1 publication Critical patent/FR2797523B1/fr
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P74/00—Testing or measuring during manufacture or treatment of wafers, substrates or devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P74/00—Testing or measuring during manufacture or treatment of wafers, substrates or devices
    • H10P74/23—Testing or measuring during manufacture or treatment of wafers, substrates or devices characterised by multiple measurements, corrections, marking or sorting processes
    • H10P74/235—Testing or measuring during manufacture or treatment of wafers, substrates or devices characterised by multiple measurements, corrections, marking or sorting processes comprising optical enhancement of defects or not-directly-visible states
FR0009956A 1999-08-04 2000-07-28 Procede d'inspection d'un substrat semiconducteur Expired - Fee Related FR2797523B1 (fr)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11221000A JP2001050874A (ja) 1999-08-04 1999-08-04 半導体基板の検査方法

Publications (2)

Publication Number Publication Date
FR2797523A1 FR2797523A1 (fr) 2001-02-16
FR2797523B1 true FR2797523B1 (fr) 2003-08-15

Family

ID=16759911

Family Applications (1)

Application Number Title Priority Date Filing Date
FR0009956A Expired - Fee Related FR2797523B1 (fr) 1999-08-04 2000-07-28 Procede d'inspection d'un substrat semiconducteur

Country Status (5)

Country Link
US (1) US6300147B1 (fr)
JP (1) JP2001050874A (fr)
KR (1) KR100347509B1 (fr)
FR (1) FR2797523B1 (fr)
TW (1) TW463377B (fr)

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW499724B (en) * 2001-05-31 2002-08-21 Taiwan Semiconductor Mfg System for dynamically monitoring the stability of machine process
JP4612659B2 (ja) * 2002-11-14 2011-01-12 株式会社東芝 半導体ウェーハの検査方法、半導体装置の開発方法、および半導体ウェーハ処理装置
US6770495B1 (en) * 2003-01-15 2004-08-03 Advanced Micro Devices, Inc. Method for revealing active regions in a SOI structure for DUT backside inspection
US6991946B1 (en) * 2003-11-05 2006-01-31 Advanced Micro Devices, Inc. Method and system for providing backside voltage contrast for silicon on insulator devices
KR100664857B1 (ko) * 2004-12-31 2007-01-03 동부일렉트로닉스 주식회사 웨이퍼 결함 분석 방법
JP2008010818A (ja) * 2006-06-01 2008-01-17 Sumitomo Electric Ind Ltd 基板、基板検査方法、素子および基板の製造方法
KR100838454B1 (ko) 2006-12-26 2008-06-16 주식회사 실트론 실리콘 웨이퍼의 전처리 방법 및 이를 이용한 점결함 농도평가 방법
US8143078B2 (en) 2009-12-23 2012-03-27 Memc Electronic Materials, Inc. Methods for monitoring the amount of contamination imparted into semiconductor wafers during wafer processing
US10127523B2 (en) * 2013-03-20 2018-11-13 Lifetime Brands, Inc. Method and apparatus for mobile quality management inspections
CN103325711A (zh) * 2013-06-27 2013-09-25 上海华力微电子有限公司 检查填充工艺中空隙的方法
CN105092619B (zh) * 2014-05-21 2017-09-26 中芯国际集成电路制造(上海)有限公司 一种芯片失效分析方法
JP6520777B2 (ja) * 2016-03-16 2019-05-29 信越半導体株式会社 シリコン単結晶ウエハの評価方法
CN113394126A (zh) * 2021-04-15 2021-09-14 上海新昇半导体科技有限公司 一种检测半导体材料中缺陷的方法

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5934629A (ja) 1982-08-23 1984-02-25 Toshiba Corp 半導体装置の製造方法
US5228878A (en) * 1989-12-18 1993-07-20 Seiko Epson Corporation Field electron emission device production method
DE4029060C2 (de) * 1990-09-13 1994-01-13 Forschungszentrum Juelich Gmbh Verfahren zur Herstellung von Bauteilen für elektronische, elektrooptische und optische Bauelemente
JPH0794688A (ja) 1993-09-21 1995-04-07 Nippon Telegr & Teleph Corp <Ntt> Ｓｏｉ 基板の製造方法
KR100197114B1 (ko) * 1995-07-19 1999-06-15 김영환 메모리 소자 집적 다이의 층결함의 3차원 검사 방법
US5780342A (en) * 1996-12-05 1998-07-14 Winbond Electronics Corporation Method for fabricating dielectric films for non-volatile electrically erasable memories
JPH10189677A (ja) * 1996-12-27 1998-07-21 Komatsu Electron Metals Co Ltd シリコンウェーハの評価方法
US5872376A (en) * 1997-03-06 1999-02-16 Advanced Micro Devices, Inc. Oxide formation technique using thin film silicon deposition
US5851892A (en) * 1997-05-07 1998-12-22 Cypress Semiconductor Corp. Fabrication sequence employing an oxide formed with minimized inducted charge and/or maximized breakdown voltage
US5972804A (en) * 1997-08-05 1999-10-26 Motorola, Inc. Process for forming a semiconductor device

Also Published As

Publication number Publication date
US6300147B1 (en) 2001-10-09
TW463377B (en) 2001-11-11
FR2797523A1 (fr) 2001-02-16
KR100347509B1 (ko) 2002-08-03
JP2001050874A (ja) 2001-02-23
KR20010021199A (ko) 2001-03-15

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Legal Events

Date Code Title Description
ST Notification of lapse

Effective date: 20080331