FR2802012B1 - Memoire dram rapide - Google Patents

Memoire dram rapide

Info

Publication number
FR2802012B1
FR2802012B1 FR9915435A FR9915435A FR2802012B1 FR 2802012 B1 FR2802012 B1 FR 2802012B1 FR 9915435 A FR9915435 A FR 9915435A FR 9915435 A FR9915435 A FR 9915435A FR 2802012 B1 FR2802012 B1 FR 2802012B1
Authority
FR
France
Prior art keywords
dram memory
fast dram
fast
memory
dram
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
FR9915435A
Other languages
English (en)
Other versions
FR2802012A1 (fr
Inventor
Michel Harrand
David Doise
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
STMicroelectronics SA
Original Assignee
STMicroelectronics SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by STMicroelectronics SA filed Critical STMicroelectronics SA
Priority to FR9915435A priority Critical patent/FR2802012B1/fr
Priority to US09/730,498 priority patent/US6631441B2/en
Publication of FR2802012A1 publication Critical patent/FR2802012A1/fr
Application granted granted Critical
Publication of FR2802012B1 publication Critical patent/FR2802012B1/fr
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G11C7/106—Data output latches
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0893—Caches characterised by their organisation or structure
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
    • G11C2207/22—Control and timing of internal memory operations
    • G11C2207/2245—Memory devices with an internal cache buffer

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Dram (AREA)
FR9915435A 1999-12-07 1999-12-07 Memoire dram rapide Expired - Fee Related FR2802012B1 (fr)

Priority Applications (2)

Application Number Priority Date Filing Date Title
FR9915435A FR2802012B1 (fr) 1999-12-07 1999-12-07 Memoire dram rapide
US09/730,498 US6631441B2 (en) 1999-12-07 2000-12-04 DRAM read and write circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR9915435A FR2802012B1 (fr) 1999-12-07 1999-12-07 Memoire dram rapide

Publications (2)

Publication Number Publication Date
FR2802012A1 FR2802012A1 (fr) 2001-06-08
FR2802012B1 true FR2802012B1 (fr) 2002-02-15

Family

ID=9552988

Family Applications (1)

Application Number Title Priority Date Filing Date
FR9915435A Expired - Fee Related FR2802012B1 (fr) 1999-12-07 1999-12-07 Memoire dram rapide

Country Status (2)

Country Link
US (1) US6631441B2 (fr)
FR (1) FR2802012B1 (fr)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004206850A (ja) * 2002-10-31 2004-07-22 Toshiba Corp 半導体記憶装置
FR2879337A1 (fr) 2004-12-15 2006-06-16 St Microelectronics Sa Circuit memoire, tel que dram, comportant un mecanisme correcteur d'erreur
US7412331B2 (en) * 2004-12-16 2008-08-12 Chevron U.S.A. Inc. Method for predicting rate of penetration using bit-specific coefficient of sliding friction and mechanical efficiency as a function of confined compressive strength

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0552667B1 (fr) * 1992-01-22 1999-04-21 Enhanced Memory Systems, Inc. DRAM avec registres intégrés
US5606532A (en) * 1995-03-17 1997-02-25 Atmel Corporation EEPROM array with flash-like core

Also Published As

Publication number Publication date
US20010023473A1 (en) 2001-09-20
FR2802012A1 (fr) 2001-06-08
US6631441B2 (en) 2003-10-07

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Legal Events

Date Code Title Description
ST Notification of lapse

Effective date: 20070831