FR2807873B1 - Procede de fabrication d'un dispositif a semiconducteur utilisant un substrat soi - Google Patents

Procede de fabrication d'un dispositif a semiconducteur utilisant un substrat soi

Info

Publication number
FR2807873B1
FR2807873B1 FR0016211A FR0016211A FR2807873B1 FR 2807873 B1 FR2807873 B1 FR 2807873B1 FR 0016211 A FR0016211 A FR 0016211A FR 0016211 A FR0016211 A FR 0016211A FR 2807873 B1 FR2807873 B1 FR 2807873B1
Authority
FR
France
Prior art keywords
manufacturing
semiconductor device
self substrate
self
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
FR0016211A
Other languages
English (en)
Other versions
FR2807873A1 (fr
Inventor
Shigenobu Maeda
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Publication of FR2807873A1 publication Critical patent/FR2807873A1/fr
Application granted granted Critical
Publication of FR2807873B1 publication Critical patent/FR2807873B1/fr
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P90/00—Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
    • H10P90/19—Preparing inhomogeneous wafers
    • H10P90/1904—Preparing vertically inhomogeneous wafers
    • H10P90/1906—Preparing SOI wafers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/01—Manufacture or treatment
    • H10W10/061—Manufacture or treatment using SOI processes together with lateral isolation, e.g. combinations of SOI and shallow trench isolations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10—Isolation regions comprising dielectric materials
    • H10W10/181—Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/01—Manufacture or treatment
    • H10W10/011—Manufacture or treatment of isolation regions comprising dielectric materials
    • H10W10/012—Manufacture or treatment of isolation regions comprising dielectric materials using local oxidation of silicon [LOCOS]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10—Isolation regions comprising dielectric materials
    • H10W10/13—Isolation regions comprising dielectric materials formed using local oxidation of silicon [LOCOS], e.g. sealed interface localised oxidation [SILO] or side-wall mask isolation [SWAMI]
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/928—Front and rear surface processing
FR0016211A 2000-04-17 2000-12-13 Procede de fabrication d'un dispositif a semiconducteur utilisant un substrat soi Expired - Fee Related FR2807873B1 (fr)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2000114963 2000-04-17

Publications (2)

Publication Number Publication Date
FR2807873A1 FR2807873A1 (fr) 2001-10-19
FR2807873B1 true FR2807873B1 (fr) 2003-10-24

Family

ID=18626684

Family Applications (1)

Application Number Title Priority Date Filing Date
FR0016211A Expired - Fee Related FR2807873B1 (fr) 2000-04-17 2000-12-13 Procede de fabrication d'un dispositif a semiconducteur utilisant un substrat soi

Country Status (5)

Country Link
US (2) US6358820B1 (fr)
KR (1) KR100355982B1 (fr)
DE (1) DE10062237A1 (fr)
FR (1) FR2807873B1 (fr)
TW (1) TW492141B (fr)

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE10015278B4 (de) * 2000-03-28 2004-09-23 Infineon Technologies Ag Halbleiterspeicher mit einem Speicherzellenfeld
US6358820B1 (en) 2000-04-17 2002-03-19 Mitsubishi Denki Kabushiki Kaisha Method of manufacturing semiconductor device
US7148553B1 (en) * 2001-08-01 2006-12-12 Davies Robert B Semiconductor device with inductive component and method of making
FR2828766B1 (fr) * 2001-08-16 2004-01-16 St Microelectronics Sa Circuit integre comprenant des elements actifs et au moins un element passif, notamment des cellules memoire dram et procede de fabrication
KR100426487B1 (ko) * 2001-12-28 2004-04-14 주식회사 하이닉스반도체 플래쉬 메모리 소자의 플로팅 게이트 형성 방법
US6798039B1 (en) 2002-10-21 2004-09-28 Integrated Device Technology, Inc. Integrated circuit inductors having high quality factors
CN1282246C (zh) * 2003-09-01 2006-10-25 上海宏力半导体制造有限公司 可阻断寄生损失电流的高功率射频集成电路及其制造方法
US6916708B2 (en) * 2003-12-04 2005-07-12 Taiwan Semiconductor Manufacturing Company Method of forming a floating gate for a stacked gate flash memory device
JP2005183686A (ja) * 2003-12-19 2005-07-07 Renesas Technology Corp 半導体装置およびその製造方法
US20110254092A1 (en) * 2010-04-14 2011-10-20 Globalfoundries Inc. Etsoi cmos architecture with dual backside stressors
JP2019121640A (ja) 2017-12-28 2019-07-22 ルネサスエレクトロニクス株式会社 半導体装置
KR102878788B1 (ko) 2021-06-22 2025-11-03 삼성전자주식회사 반도체 메모리 소자

Family Cites Families (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5120675A (en) * 1990-06-01 1992-06-09 Texas Instruments Incorporated Method for forming a trench within a semiconductor layer of material
US5145795A (en) 1990-06-25 1992-09-08 Motorola, Inc. Semiconductor device and method therefore
US5153083A (en) * 1990-12-05 1992-10-06 At&T Bell Laboratories Method of making phase-shifting lithographic masks
JP3019430B2 (ja) * 1991-01-21 2000-03-13 ソニー株式会社 半導体集積回路装置
JP3778581B2 (ja) * 1993-07-05 2006-05-24 三菱電機株式会社 半導体装置およびその製造方法
JP3257893B2 (ja) * 1993-10-18 2002-02-18 三菱電機株式会社 位相シフトマスク、その位相シフトマスクの製造方法およびその位相シフトマスクを用いた露光方法
JPH07161809A (ja) * 1993-12-02 1995-06-23 Hitachi Ltd 半導体集積回路装置およびその製造方法
DE4433330C2 (de) * 1994-09-19 1997-01-30 Fraunhofer Ges Forschung Verfahren zur Herstellung von Halbleiterstrukturen mit vorteilhaften Hochfrequenzeigenschaften sowie eine Halbleiterwaferstruktur
JP3322492B2 (ja) * 1994-11-28 2002-09-09 三菱電機株式会社 半導体装置およびその製造方法
US5670387A (en) * 1995-01-03 1997-09-23 Motorola, Inc. Process for forming semiconductor-on-insulator device
KR100233286B1 (ko) * 1996-06-29 1999-12-01 김영환 반도체 장치 및 그 제조방법
KR100201040B1 (ko) * 1996-08-26 1999-06-15 다니구찌 이찌로오; 기타오카 다카시 위상 쉬프트 마스크 및 그 제조 방법
JP3673040B2 (ja) 1996-11-12 2005-07-20 三菱電機株式会社 半導体装置およびその製造方法
JPH1174339A (ja) 1997-08-28 1999-03-16 Mitsubishi Electric Corp 半導体装置及びその製造方法
KR100281109B1 (ko) * 1997-12-15 2001-03-02 김영환 에스오아이(soi)소자및그의제조방법
US6358820B1 (en) 2000-04-17 2002-03-19 Mitsubishi Denki Kabushiki Kaisha Method of manufacturing semiconductor device

Also Published As

Publication number Publication date
US6573153B2 (en) 2003-06-03
TW492141B (en) 2002-06-21
DE10062237A1 (de) 2001-10-25
US20020072161A1 (en) 2002-06-13
US6358820B1 (en) 2002-03-19
KR100355982B1 (ko) 2002-10-12
KR20010096528A (ko) 2001-11-07
FR2807873A1 (fr) 2001-10-19

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Legal Events

Date Code Title Description
ST Notification of lapse

Effective date: 20060831